CS/A65 RAMDisk
This board uses the (now outdated) 30-pin SIMM memory modules to build a RAM disk with up to 16Mbyte. The memory is accessible via a single register, using an auto-increment byte address counter (8-bit byte address within page only).
The current status is that the board works in some specific configurations. I built the board over two years ago and encountered a number of errors (see notes below). Only recently I have tested it with the 65816 CPU board, where it works with 3 modules with 1MByte each, but not 4 modules. I still have to retest with other CPU boards and 3 modules only.
Further tests still have to be performed, but I am not sure how far I will go into this with this design version. I had a discussion with Bil Herd - yes, the designer of the Commodore 128 - who suggested some improvements:
- Use a state machine and a GAL to create a simple DRAM controller and not rely on gate delay times to create signals. I found the 8296 timing signal generation a good example for such a system.
- The board layout used could use some improvements in the layout of the power supply lines, but also the address and data lines.
- The board lacks series resistors, and termination resistors, so signal reflections could easily be a problem.
- The /RAS signal is always sent to all modules - on a CPU read or write cycle only the active module needs it. This could be a reason for the problems below, which are possibly power supply related and if all modules draw power at the same time the actual access might fail.
- Maybe even use an FPGA to implement a DRAM controller
See the this page for the full discussion
I am currently looking into a CPLD-based design for this board.
Board revisions
Version: 1.0C
Status: buggy
Notes
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With the 65816 CPU board the RAMDisk has been tested
and found working for up to 3 modules with 1MByte each.
With 4 modules certain RAMDisk addresses do not seem
to work properly. Tests with larger modules (4M) still have to be performed. |
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This is the current set of errors. The spurious counter pulses seem gone: 1) I wrote some test programs (not yet very sophisticated, but working The programs work (so far) in the lowest 64k of the RAMDisk. What I found out that there are only two addresses in a page, that give problems - $45 and $65. And that only on some of the pages, pages $1x, $5x, $9x, $dx. Interestingly the two addresses have different problems:
I don't yet know what to make of that, though. The bit pattern don't make sense to me, esp. address bits 12/13 (that seem to have to be fixed to 1/0 to give problems) and bit 5 (that seems to give problems) are handled in different ICs. 2) I scoped the supply lines for the ICs and the DRAM modules. I found a jitter of up to .3 Volts on each line (GND and VCC). So I added a .1uF multilayer capacitor to the 'LS257 that generate the multiplexed RAM address lines, and a 1u MLC in parallel to the already existing capacitors in the DRAM supply lines. The jitter did not improve much, although I had one effect: before adding the caps the problems mentioned above in 1) were also seen in addresses $47 and $67, and sometimes $44, $48, $64 and $68 - which is fixed now. |
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I have created this board by modifying the 1.0A board. Currently no layout is available. |
Files
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csa_ramdisk-v1.0c.sch |
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csa_ramdisk_v1.0c-sch.png |
Version: 1.0B
Status: buggy
Notes
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The board timing is not yet fully working. |
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This board currently has a problem with the counter on read accesses. Spurious read strobes appear that increase the counter on read accesses (but not on write accesses). I do not yet have found the source of this problem. |
Files
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csa_ramdisk-v1.0b.sch |
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csa_ramdisk_v1.0b-sch.png |
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csa_ramdisk-v1.0b.brd |
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csa_ramdisk_v1.0b-brd.png |
Version: 1.0A
Status: buggy
Notes
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The board timing is not yet fully working. |
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This board currently has a problem with the counter on read accesses. Spurious read strobes appear that increase the counter on read accesses (but not on write accesses). I do not yet have found the source of this problem. |
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The board has a timing problem. The delayed 2Phi2 signal used with RWDATA by IC6C to generate the input to IC12A comes to fast. This is fixed in V1.0B. |
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The dynamic RAM draws a lot of power. The CSA PWR board checks the supply voltage, so if this board is plugged in, the supply voltage drops below the RESET watcher threshold, and /RESET is asserted. V1.0B contains an additional power supply plug. |
Files
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csa_ramdisk-v1.0a.sch |
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csa_ramdisk_v1.0a-sch.png |
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csa_ramdisk-v1.0a.brd |
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csa_ramdisk_v1.0a-brd.png |
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ramdisk_v1.0a-1.png(On the left you can see the floppy-type power connector cable I soldered to the bottom) |
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ramdisk_v1.0a-2.png |










