CS/A65 Copro
This board implements a 6502 coprocessor board for the
CS/A65 bus system. The coprocessor runs in parallel to the
main bus CPU, with the same clock frequency as the bus itself.
The bus CPU and the coprocessor can communicate via a
64k shared memory area on the bus, as well as via a
shared control port. The port is protected against
concurrent accesses from the two cpus by optimistic
locking (explained below).
The coprocessor board has a separate bus socket where
another CS/A65 I/O board can be plugged in that the
coprocessor can handle independently from the bus I/O.
- 2006-12-16 Published the new, tested and working(!) revision of the board.
Table of content
Copro test suite
This test suite contains four tests that each use the coprocessor in a different way. The first test simply sets the shared memory to new values, the other tests use an I/O board (here a DRVIO board) to toggle I/O lines (here the two LED lines of the DRVIO board). These tests test the I/O and the interrupt abilities.
Version: 1.0B
Status: ok
Notes
This board has been fully tested in a test setup. The driver above contains the test programs. The board itself consists of two boards, where the smaller one is piggy-backed on top of the main Euro-card-sized board. The smaller one is called the "addon" board. |
Files
| csacoprodesc-v1.0b.txt | |
| csa_copro-v1.0b-sch.png | |
| csa_copro-v1.0b.sch | |
| csa_copro_addon-v1.0b-sch.png(The addon board) | |
| csa_copro_addon-v1.0b.sch(The addon board) | |
| csa_copro-v1.0b-brd.png | |
| csa_copro-v1.0b.brd | |
| csa_copro_addon-v1.0b-brd.png(The addon board) | |
| csa_copro_addon-v1.0b.brd(The addon board) | |
| copro.jpg(The complete coprocessor board; the separate wire comes from a test I made when I only thought I had a bug - which turned out to have been an incorrectly set jumper, so I fixed it to the original schematics.) | |
| copro-separated-sameside.jpg(The two coprocessor boards; note that I have used two 32k RAM chips in the tests.) |
Version: 1.0
Status: draft
Notes
| Please note that the current state of this is a draft, so there are only scanned versions of the schematics is available, and also due to its size the schematics is separated into to parts. |
Block diagram of the coprocessor board. The coprocessor
and the CS/A bus CPU access the shared memory and I/O register
using time sharing: during Phi2 the bus CPU has access, and
during Phi1 the coprocessor has access.