CS/A bus connector

The original bus connector is a 96 pin connector according to DIN 41612, type C, where only 64 pins (rows a+c) are used. The board itself has the male connector. It can be plugged into a bus plane with female connectors.

This full bus connector handles a number of signals like I2C, or memory mapping functionality that are used in some of my more sophisticated boards. These are not used in other applications, so I have created a smaller version of the connector, see below.

Wide Layout

The bus layout is:

        a       c
--------------------------
    GND a    1  c GND
   Vbuf a    2  c Vcc
   50Hz a    3  c Vcc
 -IOINH a    4  c A19
 -EXTIO a    5  c A18
-MEMSEL a    6  c A17
 -IOSEL a    7  c A16
    -BE a    8  c A15
  VCC33 a    9  c A14
 NOEXEC a   10  c A13
NOTMAPD a   11  c A12
  WPROT a   12  c A11
 I2CSDA a   13  c A10
 I2CSCL a   14  c A9
     D7 a   15  c A8
     D6 a   16  c A7
     D5 a   17  c A6
     D4 a   18  c A5
     D3 a   19  c A4
     D2 a   20  c A3
     D1 a   21  c A2
     D0 a   22  c A1
   -NMI a   23  c A0
   -IRQ a   24  c SYNC
    -SO a   25  c R/-W
    RDY a   26  c Phi2
   -RES a   27  c Phi1
    GND a   28  c Phi0
    GND a   29  c 2Phi2
    GND a   30  c 16MHz
    GND a   31  c 8Phi2
    GND a   32  c GND

Comments to V1.2

This version is unchanged in the wide connector. Version 1.2 only adds the short connector below

Comments to V1.1

The V1.1 is an upward compatible version of the V1.0 bus. The additional lines used are A9-A14
I2CSCL and I2CSDA are the I2C clock and data lines. Currently the lines are specified for a 5V I2C bus.
WPROT, NOTMAPD and NOEXEC are bus error lines. They are set when the CPU writes to a write protected page (WPROT), accesses a memory area that is marked as not mapped in the MMU (NOTMAPD), or reads an opcode on a page that is marked as not executable (NOEXEC).
The VCC33 line is a 3.3V supply line.

Comments to V1.0

For non-MMU systems like the Gecko only the lines A0-A11, D0-D7, Phi2, R/-W, -RES, -IRQ, -NMI, -IOSEL are necessary. Still some of the other lines need to be taken care of. (-MEMSEL must be pushed high).
-MEMSEL and -IOSEL are memory selection lines. If -MEMSEL goes low (active), address lines A0-A19 must be valid. If -IOSEL goes low, then only address lines A0-A11 must be valid. Both lines are not open collector lines (although this is one of the few 'known bugs' of this design)! The select lines are generated by the CPU. To map the I/O address space somewhere else (i.e. in a memory area selected by -MEMSEL), -EXTIO must be pulled low when an address in the selected area is accessed (by a memory card). Thus -MEMSEL and -IOSEL go then low on such an access.
In MMU systems, the I/O space is normally mapped to some fixed location in the CPU address space and cannot be mapped around with the MMU. To avoid this mapping, -IOINH must be pulled low. Warning: if you pull -IOINH and not do not assign -EXTIO at some address, you lose access to the I/O area. In the BIOS card for the MMU system, a control port can set these lines. -IOINH and -EXTIO are open collector lines.
Vbuf is a battery buffered 5 Volt supply. Vcc is standard 5 Volt supply, respective to GND.
50Hz is a 50/50 phase 50 Hz TTL signal, generated from line frequency. (In the U.S., you might generate it differently).
16MHz is a 16 MHz clock.
To drive some circuits synchronously with the CPU, there are 2Phi2 and 8Phi2. 2Phi2 has double the frequency than the CPU clock Phi2. At each transition of Phi2, 2Phi2 has a low-high transition. The high-low transition follows about less than 100 ns later. I use 2Phi2 to directly drive the -RAS signal of dynamic RAM.
8Phi2 is the 8-times Phi2, and this signal has a fixed phase relation to Phi2. I use it as pixel clock in a video card.
Both signals are usually generated by the CPU card.
-BE cuts the CPU off the bus, i.e. select (-IOSEL, -MEMSEL), Data (D0-7) and Address lines (A0-A19) are put into tri-state. This line is asynchronous and should only be assigned with carefully designed circuitry using -RDY stop the CPU and Phi2 for clock and all that. Using -RDY and BE should allow an external bus master to take the bus, as I have done for example in the AUXCPU board.

Short Layout

The shorter bus version is another DIN41612 of half width (type C/2), but using three rows of pins. Therefore, the bus only has 48 signals instead of 64.

The short bus layout is:

	a             b              c
-------------------------------------------------
        1 GND         1 A19          1 VCC
        2 -MEMSEL     2 A17          2 A18
        3 -IOSEL      3 A15          3 A16
        4 -BE         4 A13          4 A14
        5 D7          5 A11          5 A12
        6 D6          6 A9           6 A10
        7 D5          7 A7           7 A8
        8 D4          8 A5           8 A6
        9 D3          9 A3           9 A4
       10 D2         10 A1          10 A2
       11 D1         11 SYNC        11 A0
       12 D0         12 R/-W        12 Phi2
       13 -NMI       13 RDY         13 Phi1 
       14 -IRQ       14 VCC33       14 Phi0
       15 -RES       15 Vbuf        15 2Phi2
       16 GND        16 8Phi2       16 VCC

Comments to the short connector

The short connector allows using CS/A bus compatible cards in a space-restricted system. The need for the connector came when I designed the Ulti-PET board that fits into a C64 case, and thus needed a smaller expansion bus connector to re-use the case openings.

In general I tried to keep the signals that are most important for I/O and some boards, while removing signals that enabled special features that are, for example, only available on the old CPU with MMU board. I also kept the (mainly clock) signals that are required by the Video board, to be able to use that on the bus as well.

In principle you could remove more signals, but then it more and more starts resembling a generic 6502 bus... which is what I somewhat did on the Ultrabus backplane, but using other bus systems connectors to increase the flexibility of the bus system in general. With the Ultra-Bus board you can use (some) Apple-II, and RC2014 cards in the CS/A system.

The signals missing from the wide connector are:

-IOINH: this is used so that a board can disable mapping of the I/O window on the CPU card
-EXTIO: here a board can signal the CPU board that the I/O area should be enabled, for example at a different address range
50HZ: a 50 Hz signal originally provided by the power supply, but now obsoleted (for the PET clone) with an extra connection between CPU and PETIO boards
16MHz: a clock signal that has been proven to be of not enough quality to be used e.g. on a floppy controller board (that now has its own oscillator)
I2CSDA: I2C line. Not really used in any of the boards
I2CSCL: I2C line. Not really used in any of the boards
NOEXEC: memory mapper signal that an opcode is executed in a protected page
NOTMAPD: memory mapper signal that the CPU tries to access an unmapped memory page
WPROT: memory mapper signal indicating the CPU trying to write to a write-protected page
-SO: the CPU's "set overflow" input - not used and not even available on e.g. the 65816
GND: a number of ground signals

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Last modified: 2024-09-21