CS/A 65816 V2 CPU

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  2010-12-22 The schematics and VHDL is updated and fixed. It is now compatible to the PET816 board (with the exception of the speed register), so the same programs run on both systems.

• Making of
• Memory Map
• Control port
• Notes and possible future enhancements
• Driver
• • Simple test suite
• Board Revisions
• • 2.0E (prototype)
  • 2.0C (deprecated)
  • 2.0B (deprecated)
  • 2.0A (deprecated)
• Block diagram

When building the version 1 board I found that it is very tedious replacig parts, cutting traces and soldering new connections each time I had to test something. So I decided to try out more integrated programmable logic (more integrated than a GAL that is).

The 65816 CPU board version 2 with the PLCC CPLD logic chip.

This resulted in the CPLD programming environment giving some warnings about latches it detected, as well as combinatorial feedback loops. But yes, that's how the version 1 works, using well-placed and controlled flip-flops, and also feedback loops. So I ignored the warnings.

Using a CPLD allowed me to introduce a few more features:

• A control port to control the memory mapping (something which was very crudely done by accessing RAM3 on the version 1 board
• A more consistent memory mapping, mapping the RAM0 "under" the original 64k for write accesses
• Write protection for fast RAM in the upper ranges of the lowest 64k - so you could replace/test other ROMs
• 512k in-system-programmable Flash ROM, the lower 64k of which can be used to boot the system (jumperable)

After finding this issue, the rest of the timing issues were solved quickly by comparing what I had in the CPLD with what was working in the version 1 board.

There is one caveat though - the 2Phi2 generation is using more time in the CPLD so that it is delayed compared to the Phi2 signal. Using a 74LS14 instead of the 74ALS14 inverter as I had before delayed the bus Phi2 signal appropriately. The next step in the desig will be to integrate the clock counter and the inverter into the CPLD as well, then generating synchronized clocks, which should make the problems go away. But the first goal was the reproduction of the version 1 board with a CPLD and it worked :-)

By the way, the PET bell tone already becomes noticably faster even if you only speed up the bogus 6502 CPU cycles (which results in them not showing on the 1MHz bus).

The memory map is relatively simple, only the lowest 64k are more complicated:

Video and I/O are always mapped to the CS/A bus. The video area is mapped in the second 64k on the CS/A bus, where normally the VDC card with its video memory is located. I/O is mapped on the /IOSEL select line on the CS/A bus.

This section describes the control port for the CPU board. The port is located at $EBFF in the I/O area and is (currently) write-only (It can be relocated to $EFFF via jumper, but due to incompatibilities with my CS/A setup I decided to use $EBFF as standard location). The different bits are used as described in this table:

This section describes some notes and possible future enhancements of the board. Of the possible enhancements from version 1, actually only the too small GAL has been addressed. The following are thus mostly still from the version 1 list:

1) DRDY is only used to disable /SLOWMEM, so that RRDY is only a pulse that can be sampled at the rising edge of 8Phi2 (it has been used for other purposes in the first - faulty - design). Maybe it can be replaced with RDY.

2) The GAL has been replaced by a CPLD - ok!

3) Similar to the PET 8296 the whole timing generation could be modernized. The 8296 uses a '163 synchronous timer, the input of which is given to a small PROM, and the output of that PROM again is clocked by the 16MHz clock. This results in absolutely synchronous clock signals, which makes timing much easier. In the current design we would need a register clocked at 8Phi2 and another one at /8Phi2. This could probably be done easily in the CPLD.

4) Currently BRDY, the CS/A bus RDY line is sampled at the end of Q7, when XQ7 is sampled by 8Phi2, 65ns before Phi2 goes low. This may or may not be a problem for slow memory that uses RDY.

5) The control port was planned to be read-write, but I only managed to make it write only. This could be fixed.