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The af65002 Processor

This page describes the my af65002 implementation variant of the 65k processor architecture.

Note that the specification of the instruction set architecture (on 65k) is separate from the implementation as specified here. Also the specification and the implementation are covered under different licenses. While the documentation is under a creative commons license, the implementation here is under the LGPL (lesser general public license).

The implementation section below describes my own implementation of the 65k specs.

To my understanding the techniques described here have been used by various processors for decades already. Still there is no guarantee that a processor according to this spec would not be covered by some patents.

License

This content is licensed under the Creative Commons Attribution Share-Alike license, CC-BY-SA version 3.0.

Note this "content" includes this web page, but does not include the 6502.org header and the left and right web page columns. Click on the "Maximize" link to see the contents covered by this license.

Disclaimer

The content comes with no warranty at all! There is no guarantee and no promise that this specification is correct, consistent, will actually work, or will ever be implemented at all.

To my understanding the techniques described here have been used by various processors for decades already. Still there is no guarantee that a processor according to this spec would not be covered by some patents.

Subject to change without notice!

Contributors

Changes

This section describes the changes to the document:

DateAuthorChanges
2012-04-11André FachatInitial version

The 65002 is the first implementation of my af65k line of processors. As such it implements the basic features for af65k instruction set:

  • Wide registers and address sizes
  • Wide memory interface
  • Additional B and E registers
  • Prefix bytes to enable use of wide and more registers
  • User and Hypervisor mode
  • EXT opcode page, some SYS opcodes

Additionally the processor is compile-time configurable for 16, 32 or 64 bit wide registers, and currently 8 or 16 bit memory interface.

Here is what is notably missing:

  • Memory management / address translation
  • QUICK opcode page
  • Most of the SYS opcode page
  • No processor configuration registers (so far?)

The af65002 specification includes all the opcodes from the standard 65k opcode page, as well as the prefix1 and prefix2 prefixes. It also includes the EXT and SYS prefixes.

The exact specs are described in these pages generated from the actual processor code generator:

The 65002 architecture is described in a separate page:

The code is published on the Github site. You can either browse the code there or use git to download the code to a local repository, to be able to compile it yourself.

The code is written in VHDL.

The af65002 will share many parts of the code with other variants, as the system is very modular. As the af65k is developed further, the af65002 will inherit further features, like (if at all) more addressing modes or opcodes.

Another option is the multi-core functionality.

Naming conventions

The naming convention for the af65002 is:

    af65002Rx/yz

where x is the revision number, y is the number of cores, and z is the width notation. So for example:

    af65002R0/1W
or
    af65002R0W

is the notation of revision 0 (zero), single core, and word width (16 bit) registers.

The notation and number of cores is numeric, the width is "W", "L", or "Q" for 16, 32 or 64 bit widths.

Revision zero

The revision zero is the ongoing revision as long as I am still working on it.

Revision one

This revision will be the first "complete" revision, with all the EXT and SYS opcodes as currently defined, including the processor configuration registers.

 

No warranty! Subject to change without notice! There is no guarantee that this specification will actually work, or will ever be implemented

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Last modified: 2012-05-06
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