65002 Addressing Modes
This page describes the addressing modes for the 65k line of processors.
Table of content
The 65k is a 64 bit processor. As such the addressing modes of the 6502 are not sufficient to really use the up to 64 bit address space. Adding arbitrary new addressing modes would clutter the opcode space. So I defined a prefix bit that converts existing addressing modes into new, extended addressing modes.
Looking at the opcode table for example in this page you will notice that no new addressing modes are shown. Here the AM prefix code comes into play.
The addressing mode prefix bit AM allows to extend the existing addressing modes from zeropage (8 bit) and absolute (16 bit) to long (32 bit) and longlong (64 bit). The following table shows the modifications when AM is set.
| Original Addressing Mode | New Addressing Mode | Comment |
|---|---|---|
| zp | long | use a long (32 bit) address instead of a zeropage address |
| zp,X | long,X | use a long (32 bit) address instead of a zeropage address |
| zp,Y | long,Y | use a long (32 bit) address instead of a zeropage address |
| abs | longlong | use a longlong (64 bit) address instead of an absolute address |
| abs,X | longlong,X | use a longlong (64 bit) address instead of an absolute address |
| abs,Y | longlong,Y | use a longlong (64 bit) address instead of an absolute address |
| (zp) | [zp] | from the given zeropage location, read a long address instead of an absolute address |
| (zp),Y | [zp],Y | from the given zeropage location, read a long address instead of an absolute address, then add YR |
| (zp,X) | [zp,X] | from the given zeropage location (plus XR as given by the addressing mode), read a long address instead of an absolute address |
| (abs) | [abs] | from the given absolute location, read a long address instead of an absolute address |
| (abs),Y | [abs],Y | from the given absolute location, read a long address instead of an absolute address, then add YR |
| (abs,X) | [abs,X] | from the given absolute location (plus XR as given by the addressing mode), read a long address instead of an absolute address |
| (zp) | [[zp]] | from the given zeropage location, read a quad (longlong) address instead of an absolute address |
| (zp),Y | [[zp]],Y | from the given zeropage location, read a quad (longlong) address instead of an absolute address, then add YR |
| (zp,X) | [[zp,X]] | from the given zeropage location (plus XR as given by the addressing mode), read a quad (longlong) address instead of an absolute address |
| (abs) | [[abs]] | from the given absolute location, read a quad (longlong) address instead of an absolute address |
| (abs),Y | [[abs]],Y | from the given absolute location, read a quad (longlong) address instead of an absolute address, then add YR |
| (abs,X) | [[abs,X]] | from the given absolute location (plus XR as given by the addressing mode), read a quad (longlong) address instead of an absolute address |
| imm | imm | unchanged |
| implied | implied | unchanged |
| rel | rellong | extend the relative offset from an 8 bit to a 32 bit value |
| relwide | relquad | extend the relative offset from a 16 bit to a 64 bit value |
With a simple translation not all new addressing modes would be supported. The indirect addressing modes normally (6502) read a word address, with the AM bit set they read a long address - but for using a quad address another solution is needed. Thus the indirect opcodes are mirrored, and extended from long to quad (longlong) indirect addressing modes. Opcode Row LSB 1 is mirrored to row LSB 3, as well as row LSB 2 is mirrored to LSB 7. These values are marked with a green background in the table in the opcode structure page. The LSB 3 and 7 rows need to have the AM prefix set to 1, and use the quad (longlong) indirect addressing modes.
Also note that there a are no indirect addressing modes that take a long or quad (longlong) value as indirect address. This can be overcome with the offset prefix though.
As has been shown in the Prefixes page two prefix bits can be used to add a register value to an operand. This creates PC-relative, Stack-relative and B-register-relative addressing modes. The table from that page is reproduced here for convenience:
| OF1/0 | Register | Register Name | Syntax | Examples |
|---|---|---|---|---|
| 00 | - | no register value added | - | LDA $1234 |
| 01 | PC | Program Counter | Address prefix P, | LDA P,$1234; LDA (P,$12),Y |
| 10 | SR | Stack Pointer | Address prefix S, | LDA S,$1234; LDA [S,$23,X] |
| 11 | BR | Base Register | Address prefix B, | LDA B,$1234; LDA B,$12,X |
Note that the size of the address read from the indirect address is defined by the addressing mode alone (which is also determined by the AM prefix bit).
This section describes an overview on the addressing modes of the 65k processor. An addressing mode determines effective address of an operand (no matter what size the operand is). The addressing modes are described in detail below.
| Name | Alternative Name | Prefix | Operand Length | Syntax | Origin | Description |
|---|---|---|---|---|---|---|
| Implied | 0 | Implied by the operation | ||||
| Accumulator | 0 | Accumulator operation | ||||
| Address | 2 | abs | The parameter following the opcode is an address (16 bit; for JMP, JSR, JPU) | |||
| Address Long | AM=1 | 4 | long | 65k | The parameter following the opcode is an address (32 bit; for JMP, JSR, JPU) | |
| Address Quad | AM=1 | 8 | quad | 65k | The parameter following the opcode is an address (32 bit; for JMP, JSR, JPU) | |
| Immediate | 1 | #byte | The immediate addressing mode uses the opcode parameter directly, without further lookup. Here it is a byte parameter | |||
| Immediate 16bit | Wide immediate | RS=01 | 2 | #word | 65k | The immediate addressing mode uses the opcode parameter directly, without further lookup. Here it is a word (16bit) parameter |
| Immediate 32bit | Long immediate | RS=10 | 4 | #long | 65k | The immediate addressing mode uses the opcode parameter directly, without further lookup. Here it is a long (32bit) parameter |
| Immediate 64bit | RS=11 | 8 | #quad | 65k | The immediate addressing mode uses the opcode parameter directly, without further lookup. Here it is a quad (64bit) parameter | |
| E indirect | 0 | (E) | 65k | E-register indirect: the effective address is taken from the E register. | ||
| Zeropage | 1 | zp | Zeropage address; The effective address of the operand is a zeropage address (i.e. 8bit) | |||
| Zeropage indexed with X | Zeropage X-indexed | 1 | zp,X | Zeropage address, plus content of XR; The effective address of the operand is the opcode parameter (zeropage address), plus the value of the X register | ||
| Zeropage indexed with Y | Zeropage Y-indexed | 1 | zp,Y | Zeropage address, plus content of YR; The effective address of the operand is the opcode parameter (zeropage address), plus the value of the Y register | ||
| Absolute 16bit | Absolute | 2 | abs | 16 bit address; The effective address of the operand is the word address (i.e. 16 bit) given as opcode parameter | ||
| Absolute 16bit indexed with X | Absolute X-indexed | 2 | abs,X | 16 bit address, plus content of XR; The effective address is the opcode parameter (word address), plus the value of the X register | ||
| Absolute 16bit indexed with Y | Absolute Y-indexed | 2 | abs,Y | 16 bit address, plus content of YR; The effective address is the opcode parameter (word address), plus the value of the Y register | ||
| Absolute 32bit | Long absolute | AM=1 | 4 | long | 65k | 32 bit address; The effective address is the opcode parameter, which is a long address (i.e. 32 bit) |
| Absolute 32bit indexed with X | Long absolute X-indexed | AM=1 | 4 | long,X | 65k | 32 bit address, plus content of XR; The effective address is the opcode parameter (long address), plus the value of the X register |
| Absolute 32bit indexed with Y | Long absolute Y-indexed | AM=1 | 4 | long,Y | 65k | 32 bit address, plus content of YR; The effective address is the opcode parameter (long address), plus the value of the Y register |
| Absolute 64bit | Quad absolute | AM=1 | 8 | quad | 65k | 64 bit address; The effective address is the opcode parameter, which is a quad address (i.e. 64 bit) |
| Absolute 64bit indexed with X | Quad absolute X-indexed | AM=1 | 8 | quad,X | 65k | 64 bit address, plus content of XR; The effective address is the opcode parameter (quad address), plus the value of the X register |
| Absolute 64bit indexed with Y | Quad absolute Y-indexed | AM=1 | 8 | quad,Y | 65k | 64 bit address, plus content of YR; The effective address is the opcode parameter (quad address), plus the value of the Y register |
| Zeropage indirect 16bit | Zeropage indirect | 1 | (zp) | cmos | Load effective 16 bit address from zeropage location given; Load effective word (16bit) address from zeropage location given as parameter. | |
| Zeropage indirect 16bit indexed with Y | Zeropage indirect Y-indexed | 1 | (zp),Y | Load effective 16 bit address from zeropage location given, then add content of YR; The effective address is computed as the word (16bit) address read from the zeropage location given as parameter plus the value of the Y register. The resulting address may be larger than 16bit due to overflow when Y is added. | ||
| Zeropage indexed with X indirect 16bit | Zeropage X-indexed indirect | 1 | (zp,X) | Load effective 16 bit address from zeropage location given plus content of XR; The effective word (16bit) address is read from the location that is computed as the zeropage location given as parameter plus the value of the X register | ||
| Absolute indirect 16bit | Absolute indirect | 2 | (abs) | Load effective 16 bit address from absolute location given; The effective word (16bit) address is read from word location given as parameter. | ||
| Absolute indirect 16bit indexed with Y | Absolute indirect Y-indexed | 2 | (abs),Y | 65k | Load effective 16 bit address from absolute location given, then add content of YR; The effective address is computed as the word (16bit) address read from the word location given as parameter plus the value of the Y register. The resulting address may be larger than 16bit due to overflow when Y is added. | |
| Absolute indexed with X indirect 16bit | Absolute X-indexed indirect | 2 | (abs,X) | cmos | Load effective 16 bit address from absolute location given plus content of XR; The effective word address is read from the location that is computed as the word location given as parameter plus the value of the X register | |
| Zeropage indirect 32bit | Long Zeropage indirect | AM=1 | 1 | [zp] | 65k | Load effective 32 bit address from zeropage location given; The effective long (32bit) address is read from zeropage location given as parameter. |
| Zeropage indirect 32bit indexed with Y | Zeropage long indirect Y-indexed | AM=1 | 1 | [zp],Y | 65k | Load effective 32 bit address from zeropage location given, then add content of YR; The effective address is computed as the long (32bit) address read from the zeropage location given as parameter plus the value of the Y register. The resulting address may be larger than 32bit due to overflow when Y is added. |
| Zeropage indexed with X indirect 32bit | Zeropage X-indexed long indirect | AM=1 | 1 | [zp,X] | 65k | Load effective 32 bit address from zeropage location given plus content of XR; The effective long (32bit) address is read from the location that is computed as the zeropage location given as parameter plus the value of the X register |
| Absolute indirect 32bit | Absolute long indirect | AM=1 | 2 | [abs] | 65k | Load effective 32 bit address from absolute location given; The effective long (32bit) address is read from word location given as parameter. |
| Absolute indirect 32bit indexed with Y | Absolute long indirect Y-indexed | AM=1 | 2 | [abs],Y | 65k | Load effective 32 bit address from absolute location given, then add content of YR; The effective address is computed as the long address read from the word location given as parameter plus the value of the Y register. The resulting address may be larger than 32bit due to overflow when Y is added. |
| Absolute indexed with X indirect 32bit | Absolute X-indexed long indirect | AM=1 | 2 | [abs,X] | 65k | Load effective 32 bit address from absolute location given plus content of XR; The effective long (32bit) address is read from the location that is computed as the word location given as parameter plus the value of the X register |
| Zeropage indirect 64bit | Zeropage quad indirect | AM=1 | 1 | [[zp]] | 65k | Load effective 64 bit address from zeropage location given; The effective quad (64bit) address is read from zeropage location given as parameter. |
| Zeropage indirect 64bit indexed with Y | Zeropage quad indirect Y-indexed | AM=1 | 1 | [[zp]],Y | 65k | Load effective 64 bit address from zeropage location given, then add content of YR; The effective address is computed as the quad (64bit) address read from the zeropage location given as parameter plus the value of the Y register |
| Zeropage indexed with X indirect 64bit | Zeropage X-indexed quad indirect | AM=1 | 1 | [[zp,X]] | 65k | Load effective 64 bit address from zeropage location given plus content of XR; The effective quad (64bit) address is read from the location that is computed as the zeropage location given as parameter plus the value of the X register |
| Absolute indirect 64bit | Absolute quad indirect | AM=1 | 2 | [[abs]] | 65k | Load effective 64 bit address from absolute location given; The effective quad (64bit) address is read from word location given as parameter. |
| Absolute indirect 64bit indexed with Y | Absolute quad indirect Y-indexed | AM=1 | 2 | [[abs]],Y | 65k | Load effective 64 bit address from absolute location given, then add content of YR; The effective address is computed as the quad address read from the word location given as parameter plus the value of the Y register |
| Absolute indexed with X indirect 64bit | Absolute X-indexed quad indirect | AM=1 | 2 | [[abs,X]] | 65k | Load effective 64 bit address from absolute location given plus content of XR; The effective quad (64bit) address is read from the location that is computed as the word location given as parameter plus the value of the X register |
| Relative | 1 | rel | relative addressing modes, used in branches; from -128 to +127 | |||
| Relative 16bit | Wide relative | RS=01 | 2 | relwide | 65k | relative addressing modes, used in branches; from -32768 to +32767 |
| Relative 32bit | Long relative | RS=10 | 4 | rellong | 65k | relative addressing modes, used in branches; from -2^32 to +2^32-1 |
| Relative 64bit | Quad relative | RS=11 | 8 | relquad | 65k | relative addressing modes, used in branches; from -2^64 to +2^64-1 |
| Relative (BSR) | 1 | rel | relative addressing modes, used in BSR; from -128 to +127 | |||
| Relative 16bit (BSR) | Wide relative | 2 | relwide | 65k | relative addressing modes, used in BSR; from -32768 to +32767 | |
| Relative 32bit (BSR) | Long relative | AM=1 | 4 | rellong | 65k | relative addressing modes, used in BSR; from -2^32 to +2^32-1 |
| Relative 64bit (BSR) | Quad relative | AM=1 | 8 | relquad | 65k | relative addressing modes, used in BSR; from -2^64 to +2^64-1 |
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Last updated 2012-04-23. Last modified: 2012-04-29