The 65k Project - Future Options

• Quick Opcodes
• SYS opcodes
• FP opcodes
• Blitter opcodes
• Memory Management
• • Paged Memory Management Unit (MMU)
• Multiprocessing

These opcodes are defined by the "QUICK prefix" byte, being followed by an additional opcode byte. These opcodes may still even be modified by the prefix1 and prefix2 opcodes though!

The QUICK opcodes provide a way to "quickly" do repetitive operations which require multiple opcodes on the 6502 - like INY with an increment larger than one for example.

The following table describes the opcodes:

Here is the description of the new opcodes:

• ASR - Arithmetic Shift Right - shift right and shift in the sign of the original value from the highest bit
• RDR - Rotate Direct Right - shift right, but without using the carry flag (only setting it)
• RDL - Rotate Direct Left - shift left, but without using the carry flag (only setting it)
• SLX - shift left X by 1 to 8 bit, similar to ASL
• SRX - right left X by 1 to 8 bit, similar to ASL
• SLY - shift left Y by 1 to 8 bit, similar to LSR
• SRY - right left Y by 1 to 8 bit, similar to LSR

Note that the zp, and (E) addressing modes can be modified by the UM prefix bit, Y,X and AC related opcodes can be modified by the RS prefix. LE is not applicable as these opcodes are read-modify-write operations. All opcodes can be modified by the NF prefix.

These have been deprecated as they are redundant to ADE/SBE/ADB/SBB:

• INE - increment E register by values 1 to 8
• DEE - decrement E register by values 1 to 8
• INB - increment B register by values 1 to 8
• DEB - increment B register by values 1 to 8

This section gives an overview over the system opcodes that handle system configuration registers etc. These opcodes are all privileged.

NOTE: some of these already belong to the 65002!

Here is a short explanation of the new opcodes

• LCR - Load value from configuration register into AC. The immediate value gives the register number.
• SCR - Store value from AC to configuration register. The immediate value gives the register number.
• BCR - BIT value from AC with configuration register. The immediate value gives the register number.
• JPU - Jump to user space. Read parameter, then go from hypervisor to user mode, then read the effective address from the user mode address space (for abs indirect mode) and execute the jump
• RTU - return to user space from a Trap opcode: go to user mode, pull return address from user mode stack and execute RTS
• SENV - the byte operand determines the environment number, first variant: AC, XR and YR determine the address mask, address value and address offset registers. Second variant: the byte operand determines the environment number, E gives the memory address of the address mask, value and offset
• CLEIM - Clear EIM: load EIM bits from IMR bits; start interrupt if ISR bits have higher interrupt than EIM
• SMMU - Set the MMU base configuration address (to be defined)
• MVNTU - MVN but target is in user space
• MVNFU - MVN but source is in user space
• MVPTU - MVP but target is in user space
• MVPFU - MVP but source is in user space
• FILU - Fill user space area (i.e. use user mode match code)
• STP - Stop current core until reset (core 0) resp. enabling via core control register.
• WAI - Wait for interrupt - stops execution of current core until next interrupt

Note: these have been deprecated:

• TAI - transfer accumulator to interrupt base register (deprecated, replaced by LCR/SCR)
• TIA - transfer interrupt base register to accumulator (deprecated, replaced by LCR/SCR)
• TAT - transfer accumulator to trap vector base register (deprecated, replaced by LCR/SCR)
• TTA - transfer trap vector base register to accumulator (deprecated, replaced by LCR/SCR)
• TAU - transfer accumulator to user space stack pointer -- deprecated, replaced by TXS.U and TXS.U
• TUA - transfer user space stack pointer to accumulator -- deprecated, replaced by TXS.U and TXS.U
• SHM - Set Hypervisor Match register: Store accumulator into hypervisor mode match register (deprecated, replaced by LCR/SCR)
• SUM - Set User mode Match register: Store accumulator into user mode match register (deprecated, replaced by LCR/SCR)
• LHM - Load Hypervisor Match register: Load accumulator from hypervisor mode match register (deprecated, replaced by LCR/SCR)
• LUM - Load User mode Match register: Load accumulator from user mode match register (deprecated, replaced by LCR/SCR)
• LDA SR - Load AC from status register (can do 8 or 16 bit) (deprecated, replaced by LCR/SCR)
• LDA ISR - Load AC from interrupt status register (can do 8 bit) (deprecated, replaced by LCR/SCR)
• BIT ISR - Test interrupt status register (can do 8 bit) (deprecated, replaced by BCR)
• AND/ORA/EOR/BIT SR - operations on the status register (can do 8, 16, or 24 (zero-extended 32) bit) (no replacement)

Note: this section still needs to be worked out.

Note: this section still needs to be worked out. It is not clear if the blitter opcodes could be a not implemented column in the SYS opcodes table. Blitter opcodes would be privileged.

This section describes the memory management features of the 65k. Those features are optional. They are decoupled from the main core by the means of "match codes".

Paged Memory Management Unit (MMU)

TBD

The 65k will support multiprocessing. With the LLA and SCA it supports load-linked and store-conditional multiprocessor-safe synchronization primitives. Note that the usual read-modify write operations (ROR, ROL, LSR, ASL, ASR, RDR, RDL, INC, DEC, TSB, TRB, SLY, SRY, SLX, SRX) are in general not multiprocessor-safe. They may be multicore-safe (two cores on one processor).