Commodore PET Programming Model

•  
  2014-08-22 Added the BASIC section.

• Hardware Memory Map
• Hardware Memory Map
• I/O Area
• • $E810-$E81F - PIA 1
  • $E820-$E82F - PIA 2
  • $E840-$E84F - VIA
  • $E880-$E88F - CRTC
• Extended Models
• • SuperPET Models
  • 8x96 Models
  • 8296 Models
• Links
• • PET I/O
  • Chip Data

• BASIC 4.0 quick reference

The memory map of the PET is pretty simple - if you do not consider the 8x96 and SuperPET models. We will therefore only discuss the models up to 8032 and the other two later.

$0000-$0FFF ... $7FFF

RAM of different size. Models were shipped with 4k to 32k.

$8000-$8FFF

Screen memory. Board #1 and #2 have 1k of screen RAM, mirrored 4 times. Board #3 has (1k for 40 cols or??) 2k of RAM, mirrored 2 times. The CRTC address range is limited to the screen RAM. Board #4 uses normal CPU memory for the screen, i.e. the screen memory size is 4k. The CRTC on board #4 can address 8k, however.

$9000-$9FFF

This is an expansion ROM area. Some programs need a kind of dongle-ROM for copy protection in this socket. This was annoying when different programs needed different ROMs in the same socket...

$A000-$AFFF

This is an expansion ROM area. See above ($9000)

$B000-$BFFF

For the original ROMs and the upgrade ROMs that start at $C000, this is an expansion ROM area. See above ($9000). For the 4.0 ROMs, this is the first part.

$C000-$DFFF

BASIC ROMs (two with 4k each)

$E000-$E7FF

Editor ROM (in 4.0 ROMs, normal system ROM area otherwise)

$E800-$EFFF

I/O area (PETs without CRTC), see below. For PETs with CRTC (Fat-40 and 8032) the I/O area is 256 byte ($E800-$E8FF) and the rest is either open address or the $E*** ROM iff it is 4k.

$F000-$FFFF

Kernel ROM

The I/O area in general is 2k from $E800 to $EFFF. Used, however, is only one page ($E800-$E8FF). In the board #4 the I/O size has been reduced to this page, allowing for more ROM space in $E900-$EFFF for nationalized keyboard mappings.

The decoding has been done with minimal effort: The address lines A4-A7 are each directly used to select an I/O chip. Bit A4 must be set for the PIA 1, A5 must be set for PIA 2, A6 must be set for the VIA and A7 must be set for the CRCT (if available). This results in some addresses where more than one chip is selected. When reading them, all selected chips drive the data bus. As these chips have NMOS drivers, they should produce a wired-and of all chip outputs, but this is not always the case and may depend on other bus loads or whatever. Below only the normal mappings are described. For the exact description see the petio file.

$E810-$E81F - PIA 1

PIA 1 is used for the keyboard, some tape I/O and the IEEE488 EOI line. Also CB1 is used to generate the system interrupt - it is connected to the screen vertical blank signal and can generate IRQs on level transitions.

Use of PIA 1 signals in a PET:
------------------------------
PIA 1

E810    PORT A  7   Diagnostic sense (pin 5 on the user port)
                6   IEEE EOI in
                5   Cassette sense #2
                4   Cassette sense #1
                3-0 Keyboard row select (through 4->10 decoder)
E811    CA2         output to blank the screen (old PETs only)
                    IEEE EOI out
        CA1         cassette #1 read line
E812    PORT B  7-0 Contents of keyboard row
                    Usually all or all but one bits set.
E813    CB2         output to cassette #1 motor: 0=on, 1=off
        CB1         screen retrace detection in. This input is used to
                    generate the 50 or 60 Hz IRQ. Also connected to
                    VIA PB5.

$E820-$E82F - PIA 2

PIA 2 has the 8 IEEE488 data lines (in and out) and some IEEE488 control lines.

Use of PIA 2 signals in a PET:
------------------------------
PIA 2

E820    PORT A      Input buffer for IEEE data lines
E821    CA2         IEEE NDAC out
        CA1         IEEE ATN in
E822    PORT B      Output buffer for IEEE data lines
E823    CB2         IEEE DAV out
        CB1         IEEE SRQ in

$E840-$E84F - VIA

Use of VIA signals in a PET
---------------------------
E840    PORT B  7   DAV in
                6   NRFD in
                5   screen retrace in (also connected to PIA1 CB1)
                4   cassette #2 motor (note 2)
                3   cassette write data out
                2   ATN out
                1   NRFD out
                0   NDAC in
E841    PORT A      USER PORT with CA2 handshake (note 1)
E842    DDRB    7-0 normal bits set to 0 0 0 1 1 1 1 0
E843    DDRA    7-0 USER PORT data direction register
E844    Timer 1 LO
E845    Timer 1 HI  (set to $FF on system power-on)
E846    Timer 1 latch LO
E847    Timer 1 latch HI
E848    Timer 2 LO
E849    Timer 2 HI
E84A    Shift register
E84B    ACR     Aux. control register; set to $00 at power on
                7-6 timer 1 control
                5   timer 2 control
                4-2 shift register control
                1   port B latch
                0   port A latch
E84C    PCR     Peripheral Control Register; set to $0C or $0E at power on
                7-5 CB2 control (user port pin M) (note 3)
                4   CB1 control (note 3)
                3-1 CA2 control (graphics mode) (note 3)
                0   CA1 control (note 3)
E84D    IFR     Interrupt Flag Register; set to $00 at power on
                7   IRQ on/off
                6   T1 interrupt flagged
                5   T2 interrupt flagged
                4   CB1 interrupt flagged
                3   CB2 interrupt flagged
                2   shift register interrupt flagged
                1   CA1 interrupt flagged
                0   CA2 interrupt flagged
E84E    IER     Interrupt Enable Register; set to $80 at power on
                7   1=enable, 0=disable
                6-0 enable interrupts; same bits as in IFR.
E84F    PORTA       USER PORT without CA2 handshake

Note 1: E84F is the preferred user port register, since CA2 controls screen
graphics.

Note 2: The motor is on when this line is low, and off when it is high.

Note 3: CA1 is connected to pin B of the user port. Pins B-L correspond to
port A, which is invariably E84E. CB2 (connected to the shift register) also
connects to pin M of the user port; square wave tones (see chapter 9 of
"Programming the PET/CBM") use these facts. CB1 signals input from cassette
#2. CA2 controls screen graphics: it is configured for output, and, when
low, gives lower case characters and others. When high, the mode is upper
case and graphics.

$E880-$E88F - CRTC

The CRTC is only available in newer PETs, with the boards #3 and #4. It has only two registers, one to write the internal register number to and one for the internal register value. In the following only the internal register numbers will be used.

The 6545 is a very flexible chip. It can be programmed very freely to different video timings. In fact it has been used in early PC video cards and VGA cards still have an emulation of the 6545 registers. For a complete description please have a look at the CRTC docs or a description on the CRTC operations. I will now only go into the PET specifics, that I read from the schematics.

The 6545 has 14 address lines (VA), allowing up to 16k of video memory to be addressed. In the PET, however, not all of them are used. All PETs with CRTC (except 8296) only use VA 0-9 the 1k video area. The 80 cols PET also only use these addresses, as the they are here used as A1-A10. Two bytes are read simultaneously from the two video RAM chips (1k each) during each clock cycle, allowing for the higher character rate. (I have not found out how the 8296 does that, because it uses normal CPU RAM for the video output). So the 80 cols PET set their screen width to 40 in the CRTC too. As the character counting only counts up to 1k the upper bits of the screen address (that can be set in the CRTC) are unchanged and used for control here (i.e. VA12 and VA13; VA10 and VA11 are unused).

VA12 is used to invert the complete video signal after blanking the off-screen areas. Changing this signal would switch on the electron beam during the retrace times, i.e. one would see the `flyback'.

VA13 is, probably more importantly used as another address line for the character generator ROM. This is probably used for nationalized character sets?

The screen memory is read with the addresses given from the CRTC. The value read is then given to the character generator ROM as address and the output is fed to the video shift register. Only seven bits from the memory are used as character ROM addresses, the 8th bit is used to invert the character by hardware!

One character normally consists of 8 scanlines and during each of the scan lines the CRTC provides the same address, only its RA 0-4 count the scan lines. RA 0-2 are given the the character generator ROM to display a different byte for each scan line. On the CRTC PET the upper/lower case mode sets the number of scan lines to 9 (or 10?) though. But the hardware automatically blanks the displayed character for all scan lines above the 8th...

SuperPET Models

The SuperPET also known as MicroMainFrame 9000, esp. in Europe, has an extension board with a 6809 CPU, but also with additional I/O. In particular the SuperPET has an ACIA to implement a serial (RS232) interface. More details are on the SuperPET page here.

• SuperPET Page

8x96 Models

The 8032 with 64k expansion board - which is the same as the 8096 model introduced memory mapping the upper 32k. Therefore a new write-only register was created, at $FFF0. By writing certain values into it, two 16k areas from $8000-$BFFF and $C000-$FFFF can be mapped to two different expansion memory blocks each, giving up to 64k expansion RAM. The screen memory ($8000-$8FFF) and the I/O area ($E800-$EFFF) can be excepted from the mapping. Also the pages can be mapped read-only.

The memory mapping can be seen in this image.

As ROM the 8x96 models have the standard 8032 4.0 ROMs. Only they can run the LOS-96 operating system, an improved BASIC version.

The description of the $FFF0 register is included in the 8096 addendum in the petio text.

• 8x96 Page

8296 Models

The 8296 includes the 8096 memory mapping in its own hardware already. Its RAM is organized in 2 banks of 64k, where the second bank is used as expansion RAM. The lower half of the first bank is used as normal RAM, the second half is mapped write-only under the ROM. Only the screen memory ($8000-$8FFF) is mapped read/write. By setting certain jumpers on the hardware the expansion ROM areas ($9000-$9FFF and $A000-$AFFF) can be switched off, mapping the RAM from the first bank there.

The CRTC in the 8296 uses the video address lines VA 0-11, giving 8k of addressable (they are used as A1-A12 in 80 cols models!) video RAM. Only VA 12 is still used to switch the character ROM. The lower 4k ($8000-$8FFF) are usable anyway, only the upper 4k ($9000-$9FFF) can be used write-only without jumper settings or read/write with a jumper set (see petio text.

A full memory map of the CBM8296 is in this image.

• 8x96 Page

PET I/O

• petio.txt

Chip Data

• 6502 programming info from the VICE team
• 6522 documentation
• Chipdata on the CBM archive
• Chip datasheets on 6502.org