CRTC operation
(C) 1998-2010 André Fachat
The 6545/6845 Cathode Ray Tube Controller (CRTC) is a flexible video chip. It has been used in the Commodore PET computers, and even early PC graphics cards.
For the operation of the video interface Commodore introduced the Cathode Ray Tube Controller (CRTC) 6545 with the third type of boards. This controller is very flexible, programmable and provides all necessary interface signals for the video hardware.
I have made a collection of test programs and timing examples for the CRTC in my CBM 8296. You can download the whole suite, including a (derived) diagram of the CRTC internals from the CBM archive as crtctest-1.1.tar.gz. It also includes a summary of the differences of the various CRTC models. You can have a look at some of the weird screen distortions in the test program documentation, and an overview over the derived CRTC internals on this page (all from the crtctest archive).
A sample schematic can be found on the CS/A65 computer page or in the PET schematics on the links page of the PET index.
- 2013-11-02 Added the C64 80 column card description, as well as the hires mode description.
- 2010-12-20 Separated from the main CRTC page.
Table of content
There are a few things that might be different from other implementations in the PET. The CRTC has been used in 40 columns and 80 columns models. The CCLK frequency however is 1 MHz in both cases. 80 columns mode is achieved by reading not one byte but two byte in each CCLK cycle with the same MA0-13, thus effectively using the MA0-9 as A1-10.
As only MA0-9 are used, Commodore decided to use the uppermost two bits (MA12 and MA13) as additional control lines. MA12 is used to invert the complete pixel stream video output, probably to be able to cope with different video hardware. MA13 is used as an additional A11 to switch the 2k halfs of a newer 4k charrom. This is used for nationalized character sets?
Only seven bit of the data read from memory are used for character ROM addressing. The 8th bit is instead directly fed to an inverter, inverting the pixel stream if set - thus inverting the character.
The Cursor hardware is not used.
If more than 8 scanlines per character are used the hardware automatically blanks the scanlines for the scanlines beyond the 8th. Without that and only RA0-2 used for character ROM address the same character would be redisplayed from the start.
PET 4032 'Fat40'
The so-called 'Fat40' is a 4032 model that has a 12" screen and a "universal board" - a board that can be used for the 8032 or the 4032. Thus it uses the CRTC as video chip. A separate static memory separate from main memory is used as video RAM.
PET 4032 CRTC usage block diagram
---------------------------------
| CRTC |
---------------------------------------------------------------------------
MA0-9 | RA0-2 | ------- DE|
| | | | |
| ----- ------- -----|A0-2 | ----- | ---
| | | | | ----- | |D0-7 | | --- +--| | Video
+--| | A0-9 | | D0-7 | | D0-6 | |------| |-----| | |>|---
| > |------| RAM |---+---| |---+-----|A3-8 | | | | |-----| |
CPU A0-9 -----------| | | | | | | | | | ----- +-| | ---
| | | | | ----- | ------- shift | --- AND
----- ------- | Latch | Charrom register | XOR
Mux 2-to-1 | |D7 |
| +--------------------------+
----- |
| | |
CPU D0-7 -----------| |----------------+
| |
-----
Buffer
During Phi2 low (Processor does not use the bus) the Mux chip selects the MA0-9 address lines from the CRTC. The video RAM then outputs the character value and it is saved in the latch. The latch output is then used as input for the Charrom. The output of which is given to the shift register that makes a pixel stream rather than a byte stream.
When Phi2 is high then the Mux selects the CPU address lines for the video RAM, allowing normal CPU memory accesses.
The Vertical Sync signal of the CRTC is not only used for video hardware control but it is also (inverted and) connected to the PIA1 CB1 line to generate system interrupts with the frame rate. Also the state of this line can be checked with VIA PB5.
PET 8032
The universal board can also be used in the 8032. As the 8032 also runs on 1MHz only, there is a problem with the memory bandwidth. The memory used was static RAM with a maximum access frequency of 2MHz. As half the cycles were reserved for the CPU (Phi2 high), only 1MHz video RAM bandwidth was left, which is only enough for 40 columns a line - with an 8 bit graphics data bus.
In the 8032, however, Commodore decided to use a 16 bit graphics data bus. How does this work? The video memory is separated into to areas of 1kByte each, that the CPU can write to independetly with 8 bit access. One area is for even addresses, the other for odd CPU memory addresses. The video circuitry, however, reads both the RAM areas at the same time (thus twice 8bit = 16bit access), and latches both values. To generate the video signal than first the value from the even area, then the one from the odd area is used.
PET 8032 CRTC usage block diagram
---------------------------------
| CRTC |
-----------------------------------------------------------------------------
MA0-9 | RA0-2 | ------- DE|
| | | | |
| ----- ------- even +----|A0-2 | ----- | ---
| | | | | ----- | |D0-7 | | --- +--| | Video
+--| | A0-9 | even| D0-7 | | D0-6 | |------| |-----| | |>|---
| > |---+--| RAM |---+-----| |-+-+-----|A3-8 | | | | |-----| |
CPU A0-9 -----------| | | | | | | | | | | | ----- +-| | ---
| | | | | | ----- | | ------- shift | --- AND
----- | ------- | Latch | | Charrom register | XOR
Mux | | | | D7 |
2-to-1 | | | +--------------------------+
| ------- | odd |
| | | | ----- |D0-7
| | odd | | | | |
+--| RAM |--/|\-+--| |-+
| | | | | |
| | | | -----
even ------- | | Latch
----- | |
| | | |
CPU D0-7 ------+----| |----------------- |
| | | |
| ----- |
| odd |
| ----- |
| | | |
-----| |-------------------+
| |
-----
Buffer
This diagram shows how the RAM and latches are doubled for even and odd addresses. It also makes it clear that it is a relatively simple addition to the 4032 to display 80 columns. This is one reason why universal boards are actually feasible.
This setup also explains why even the 80 columns PET actually initialize the CRTC video chip with 40 columns - as the video RAM bus width is 16bit instead of 8bit, each of the CRTC character actually is two characters on the screen.
PET 8296
The 8296 is a different beast altogether. Here the separate static video memory is completely gone. All the memory of the system (actually 128k, of which 96k can be used as main memory and 4k as video memory) is put into two dynamic RAM banks of 64k each.
PET 8296 CRTC usage block diagram
---------------------------------
| CRTC |
-----------------------------------------------------------------------------
MA0-9 | RA0-2 | ------- DE|
| | | | |
| ----- ------- even +----|A0-2 | ----- | ---
| | | DRM | | ----- | |D0-7 | | --- +--| | Video
+--| | 0-7 | 64k | D0-7 | | D0-6 | |------| |-----| | |>|---
| | > |---+--| RAM |---+-----| |-+-+-----|A3-8 | | | | |-----| |
+--| | | | | | | | | | | | ----- +-| | ---
| | | | | | ----- | | ------- shift | --- AND
----- | ------- | Latch | | Charrom register | XOR
Mux | | | | D7 |
2-to-1 | | | +--------------------------+
----- | ------- | odd |
| | | | | | ----- |D0-7
+-----| | | | 64k | | | | |
CPU A0-15 ----+ | > |---+--| RAM |---+-----| |-+
+-----| | | | | | |
| | | | | -----
----- ------- | Latch
|
----- |
| | |
CPU D0-7 -----------| |-----------------
| |
-----
As opposed to static RAM, dynamic RAM requires multiplexed address lines. Therefore both, the CPU and CRTC address lines are multiplexed separately with 74ls257 ICs that are enabled only when the CPU or CRTC respectively accesses the memory.
The diagram shows that now the dRAM address and data lines are shared between the two 64k memory banks. This means that only one access can happen at a time. as a result, to display 80 columns, it is necessary that the memory is accessed faster than 2MHz. In fact it is accessed faster, with approx. 4Mhz, as can be seen in the description of the UC2 PLA logic equations in 8296desc.txt.
Steve Gray's Colour PET
Steve Gray has come up with an ingenious way of converting a green/black 80 column PET into a 40 column colour PET! In each cycle the 80 column PET reads two bytes, as described above. Steve now uses the first byte for normal display, just with 8MHz pixel clock, and the second byte is used to define the colours for the on and off bits.
Colour PET CRTC usage block diagram
---------------------------------
| CRTC |
-----------------------------------------------------------------------------
MA0-9 | RA0-2 | ------- DE|
| | | | |
| ----- ------- even +----|A0-2 | ----- | ---
| | | | | ----- | |D0-7 | | --- +--| | Video
+--| | A0-9 | even| D0-7 | | D0-6 | |------| |-----| | |>|------+
| > |---+--| RAM |---+-----| |-+-+-----|A3-8 | | | | |-----| | |
CPU A0-9 -----------| | | | | | | | | | | ----- +-| | --- |
| | | | | | ----- | ------- shift | --- AND |
----- | ------- | Latch | Charrom register | XOR |
Mux | | | D7 | |
2-to-1 | | +--------------------------+ +-------------+
| ------- | odd |
| | | | ----- ----- -----
| | odd | | | | | | +--| |
+--| RAM |--/|\-+--| |----------| |--------------+ | |----- RGBI output
| | | | | | | | +--| |
| | | | ----- ----- -----
even ------- | | Latch delay select foreground/
----- | | latch background colour
| | | |
CPU D0-7 ------+----| |----------------- |
| | | |
| ----- |
| odd |
| ----- |
| | | |
-----| |-------------------+
| |
-----
Buffer
The difference to the main 80 column PET is that the data from the odd latch is not given to the character ROM, but stored in the latch and given to a 2-to-1 multiplexer. This multiplexer selects either the upper or the lower nibble of the stored data byte by using the video bit stream as selector. It then outputs them as RGBI foreground or background colour. This results in a 8x8 pixel array that have the same foreground and background colour (notwithstanding carefully timed changes to the colour RAM as was often done on the C64 :-).
Some caveats: The RAM address muxes must be set to a 40 column model ta achieve a continous video RAM in $8000-$83ff and a colour RAM in $8400-$87ff. The pixel clock must also be set to the 40 column model's 8 MHz and not the 80 column model's 16 MHz.
The delay between reading the data and actually shifting it out must also be taken into account by using some delay latch. Otherwise the shifted data changes colour when the next data byte is being read from the RAM.
C64 80 column card
Bil Herd has found a set of schematics - for the C64 80 columns card. This card also uses a CRTC - but the schematics show an interesting quirk: the C64 does not have access to the video RAM! Well, at least not directly. It uses the transparent addressing mode available in the 6545-1. I.e. the CRTC always generates the video RAM addresses, but the CPU can access the video RAM via separate data bus buffers.
Colour PET CRTC usage block diagram
---------------------------------
| CRTC |
----------------------------------------------------------------------------------------
RA4| MA0-9| CE| RA0-2 |
| | | +--+ | -------
| | +----| |XOR | | |
| | ------- D7+-| |-+ +----|A0-2 | -----
| | | | | +--+ | ----- | |D0-7 | |
| | A0-10 | | D0-7| | | | D0-7 | |------| |-----
| +----------+--| RAM |---+-+------+---| |---------|A3-8 | | |
| | | | | | | | -----
| CPU | | | ----- ------- shift
+--+-----+ ------- | Latch Charrom register
| | read |
| | ----- |
| +---| | |
CPU D0-7 ---/|\---+----| |-------------+
| | | | |
| | ----- |
| | write |
| | ----- |
| | | | |
| -----| |-------------+
+---------| |
-----
Buffer
This schematics works, as mentioned with the CRTC creating the video address for the CPU access. To achieve this the CPU sets the address it wants to access into registers 18 and 19 in the CRTC. The CRTC then waits for an appropriate time and puts a latch on the RA4 line that is used as update strobe. This enables data transfer with the read or write buffers (the schematics here is simplified. Write buffer control is via a PLA).
Another interesting quirk is the cursor generation. The cursor can be automatically enabled by the CRTC (other than in the PET). Other than inverting the data from the character ROM the uppermost bit of the data read from RAM is inverted! This means you select a different page of the character ROM, not just the same inverted character from ROM. Thus you could switch between two completely different characters - if you were to use a custom character ROM. Of course the character ROM just had the inverted character in it (but still leaving open whether the character is optimized for inverted display).
Another interesting point is the display enable handling. The DE line controls whether the shift register is loaded. If DE is disabled, the character ROM is not loaded from the character data anymore and just displays the data from the serial in pin - meaning blank video.
What is not shown here is a separate control register that allows to invert the video output (REVSCN), select a second character set in the charrom (SETSEL), and a 40/80 column switch - that switches between the 80 column output from above and a through-connected video input (connected from the C64's VIC video output via separate cable).
Hires modes
The CRTC is made for character-based display. To use it for hires graphics therefore some tricks need to be done.
- The normal display has over 512 raster lines. The CRTC can only do 128 character lines - thus a graphics mode cannot just set one character line per raster lines.
- The graphics RAM output is normally passed through the character ROM - but for graphics the data must be passed through unchanged
The following diagram shows one way to achieve hires mode:
- The uppermost video address bits are replaced with the RA0 and RA1 lines (via a 2-to-1 mux so you can still use the original setup). This makes for an interleaved memory layout. The first rasterline for each character is in the first 4k RAM, the second rasterline is in the second 4k RAM, until the fourth rasterline is in the fourth 4k RAM. A character line is set to 4 rasterlines only, so that the fifth rasterline is back in the first 4k RAM, but in the next character line. With this setup each character position / rasterline in character combination has its own byte stored in RAM, so that each position can be controller individually. Setting the character line to four rasterlines also allows to have the 512+ rasterlines with only up to 128 character lines as the CRTC allows.
- The character ROM has a special mapping - a one-to-one mapping that just passes through each input byte as output byte. Each input byte from 0-255 is mapped multiple times, as the RA0/1 lines are still connected to the character ROM.
Hires modes
-----------
| CRTC |
----------------------------------------------------------------------------------------------
MA12/13| MA0-11 | RA0-2 | DE|
| RA0/1 | | |
| +------------/|\------------------------------------+ |
| | ----- | | |
| +-| | | | ------- |
| | > |----+ | | | | |
+----| | | | ----- ------- -----|A0-2 | ----- | ---
----- | | | | | | ----- | |D0-7 | | --- +--| | Video
Mux 2-to-1 +--+--| | A0-13 | | D0-7 | | D0-6 | |------| |-----| | |>|---
| > |-------| RAM |---+---| |---+-----|A3-8 | | | | |-----| |
CPU A0-13 -----------------| | | | | | | | | | ----- +-| | ---
| | | | | ----- | ------- shift | --- AND
----- ------- | Latch | Charrom register | XOR
Mux 2-to-1 | |D7 |
| +--------------------------+
----- |
| | |
CPU D0-7 ------------------| |-----------------+
| |
-----
Buffer
The schematics shown here is - in principle, the card uses dRAM with extra MUXes - the one as used in the CS/A65 video card. Incidentially the IBM PC CGA graphics card uses a similar scheme, with just RA0 switching between two 8k memory banks.
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Last modified: 2013-11-02