Now for the innards of the box labeled "carry chain":
(I'm also showing the XOR gates connected to the outputs of the carry chain)

I guess, that them engineers who designed that IC
were a little bit paranoid when disabling the entire
carry chain if CEN=0.

Of course, in the datasheet things look more complicated
and a little bit different. We may find AND NOR combination
gates, XNOR gates and such.

But for better readibility of the pictures, I decided to draw
the schematics with AND/OR combination gates and XOR
gates instead.

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(c) Dieter Mueller 2012