First, the RX signal goes into a 'digital' filter.
RX has to be stable for three clock cycles to be latched into the flipflop
that emits RX1 towards the Start Bit detection and the RX shift register.
(Keep in mind, that the clock runs 16 times faster than the baud rate.)
The basic idea is, that an interfering signal shorter than three clock
cycles might be ignored, so there is a chance that the Start Bit
detection won't trigger the receiver by accident.
The 74164 shift register samples the RX signal, and the 74151
8:1 multiplexer uses three succesive Bits from said shift register
to figure out what to do with the RX1 flipflop.
So much for the filter.
Since a Start Bit is represented by a 0 on RX1
(and the previous Stop Bit made sure that RX1 was 1 before),
we use a second flipflop to latch the previous level on RX1, what gives us RX2.
If RX1 (actual value) is 0, and RX2 (previous value) is 1,
then the NAND gate makes sure that the receiver will start to receive/operate
at the next rising edge on CLK.
Problem is, that the circuitry would _always_ try to trigger to a falling edge on RX1:
if one would transmit 0x55, there are 5 falling edges (including the Start Bit) on the RX1 line.
To prevent the received Data from being shredded apart by re_triggering the receiver
during the reception of a Byte,
we just pretend that the previous value was 0 by keeping the RX2 flipflop cleared
when the receiver is running...
what is indicated by RDONE = 0.
The control circuitry of the receiver is based on the idea used for the
transmitter.
But now we have two 74163 counters:
one to count the received Data Bits,
and one to count the cycles of a Bit.
If the cycle counter rolls over, the Bit counter is incremented until it reaches 15.
Then all of the Data Bits are received, both counters are stopped at 15,
and RDONE goes high.
The /RSTART signal from the Start Bit detector loads/starts both counters,
what takes one clock cycle...
so we're loading the cycle counter wit 1 to compensate that.
The uppermost Bit from the cycle counter gives us a neat/clean rising edge
in the middle of a Data Bit, so we use it to clock the receive shift register.
There could be some dirt on the RDONE signal, so we better synchronize
it to the clock before we use it to transfer the received Byte from
the receive shift register into the 'receive hold register'.
We also have a 'status register', built with two flipflops (you could
as well use a 74164 instead), that is clocked at the same time as the
'receive hold register'.
Data input of this shift register is set to 1, so if a valid Byte is in the
'receive hold register', RX_VALID is set to 1, indicating that the CPU
or microcontroller in control of the UART can read out said Byte...
what will clear the status register.
If it takes too long to read the Byte, the contents of the
'receive hold register' might be overwritten by the next Byte received,
and the OVERFLOW flipflop indicates that your Data stream
went corrupted.
Some UARTS also sample the Stop Bit, that is supposed to be 1,
and set a 'frame error' flag if said Bit was 0...
indicating that something is wrong with the configuration of the UART:
wrong Baud Rate, or wrong number of Data Bits.
There are some other tricks to build a simpler RX circuitry,
but they are probably less reliable...
...and maybe limited to a fixed Baud Rate when using 74221 monoflops.
BTW: You might want to take a look at the 'Imlac' schematics:
an old computer that also had a 74xx TTL based UART.
Good luck when building your own UART, and please put a photo
of your contraption in the Internet when you had success.
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(c) Dieter Mueller 2007