So far, the TREX CPU only supports indirect addressing,
immediate addressing is just a special form which uses PC
as address register (and increments PC after fetching the word).

For the rest of the addressing modes, you would have to define
some assembler macros...

To simplify things, the examples in this articles don't make
use of the "don't modify Flags" option. Take care !

Immediate/literal addressing:

 R2=[PC++], nop, nop;          //R2=#
 .word LITERAL_VAL_FOR_R2;

The example above loads a 32 Bit word into R2.
You could modify it for adding a value to R2:

 R6=[PC++], R2+=R6, nop;       //R2+=#
 .word LITERAL_VAL_ADDED_TO_R2;

Loading three literal values:

 R2=[PC++], R3=[PC++], R4=[PC++]; //R2=#, R3=#, R4=#
 .word LITERAL_VAL_FOR_R2;
 .word LITERAL_VAL_FOR_R3;
 .word LITERAL_VAL_FOR_R4;

Pushing a literal value on stack:

 R6=[PC++], SP--, [SP]=R6;  //[--SP]=#
 .word LITERAL;

since we are at it, you could pop the value
from stack like this:

 R2=[SP], SP++, nop; //R2=[SP++]

Absolute addressing:

 R6=[PC++], R2=[R6], nop; //R2=[ABSOLUTE_ADDRESS]
 .word ABSOLUTE_ADDRESS;

Indirect addressing:

 R6=[PC++], R6=[R6], R2=[R6]; //R2=[[ABSOLUTE_ADDRESS]]
 .word ABSOLUTE_ADDRESS;   

Base register with offset:

 R6=[PC++], R6+=R2, R3=[R6]; //R3=[R2+OFFSET]
 .word OFFSET;

Al of the above:

 R6=[PC++], R4=[PC++], R6+=R3;  //R2=[[ABSOLUTE_ADDRESS+R3]+OFFSET]
 R6=[R6],   R6+=R4,    R2=[R6]; //(uses R4 as scratchpad)
 .word ABSOLUTE_ADDRESS;
 .word OFFSET;

From here on, you should be able to build/define your own
"addressing modes".

So it's possible to "emulate" high level CISC addressing modes
as known from the 68000 with one to three 32 Bit instruction words,
plus parameters.

68k would need one to two 16 Bit words for the instruction,
plus one or two 16 Bit words for addres or data.

Since TREX has a 32 Bit data bus, performance compared to the
68000 doesn't look too bad.

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(c) Dieter Mueller 2007, 2008