Registers


TREX register set: all registers are 32 Bit wide.

    --------------------------------
R0 | O31..O16     | I15..I4    |NVZC| SR, Status Register
    --------------------------------
R1 |                                | SP, Stack Pointer
    --------------------------------
R2 |                                |
    --------------------------------
R3 |                                |
    --------------------------------
R4 |                                |
    --------------------------------
R5 |                                | LA, Loop Address
    --------------------------------
R6 |                                | LR, Link Register
    --------------------------------
R7 |                                | PC, Program Counter
    --------------------------------

PC/R7, the Program Counter,
points at the next instruction word to be fetched.

So any instruction which writes PC causes a change in program flow.

For instance, moving a literal value into PC with PC=[PC++] is equivalent
to a JMP or JSR instruction, like known from other CPUs.

LR/R6, the Link Register,
basically is a scratchpad area for address and data calculations.

If an instruction writes a value into PC, the old contents of PC are
always saved into LR, so a called subroutine is able to save "return address"
in LR on stack for restoring it into PC later.

(Some care must be taken to prevent interrupts from corrupting LR.)

LA/R5, the Loop Address,
is written into PC when the CONT instruction is true.

A feature, which might be useful for building small/tight loops.

Besides that, LA/R5 can be used as a general purpose register.

R4, R3, R2 are general purpose registers.

SP/R1 is used as Stackpointer.

From the hardware point of view, R1 is nothing more/less than just
another general purpose register. The assembler/compiler uses R1 as SP by definition, so it's only
a software thing.

SR/R0 is the Status Register.

As with other CPUs (like 68k), Bits 0..3 represent the Flags N,V,Z,C.

Bits 4..15 are twelve input lines from outside the CPU, which might
be checked by the SKIP/CONT instruction.

Bits 16..32 are sixteen output lines, available outside the CPU.

You may see Bit 4..31 as sort of a very fast I/O port.
If the CPU doesn't support interrupts, it's possible to poll signals
from the peripherals fast by software.
When adding sort of a MMU to the design, 16 Bits are supposed to be
enough to select/identify a program/task, and to support something like
a user/supervisor mode, as known from the 68k.

For better MMU support, there are two control signals which can block
a software write to Bit 16..23 and Bit 24..31.

Bug warning: TREX CPU rev.1 is unable to write the contents of SR
directly into memory. Thou shalt transfer SR into another register,
then write said register to memory instead.

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