MEMORY PLUS Manual By Lee Davison
Page 10
VERSATILE INTERFACE ADAPTER
The 6522 Versatile Interface Adapter is one of the important pluses of
MEMORY PLUS. This sophisticated chip has the following basic features:
I/O: Two 8-bit parallel I/O ports with additional handshaking
control lines. This more than doubles the basic KIM-i
I/O capabilities.
TIMERS: Two powerful interval timers which have a number of
operating modes permitting them to be used as counters1
"free-running" timers, "one-shot" timers, and more.
SHIFT REGISTER: Perform serial I/O under control of a timer, the
system clock or an external signal. Serial-to-parallel and
parallel-to-serial conversions take place within the 6522
without involving the MICRO on a bit-by-bit basis.
INTERRUPTS: The many different devices on the 6522 can cause
interrupts to signal the completion of activity. These
interrupts can be individually enabled, disabled and
tested.
The 6255 chip has two functions on MEMORY PLUS. The first is to provide all
of the 6522 capabilities to the user as an extension of the MICRO. The
second is to control the EPROM Programmer. The 6522 is the heart of the EPROM
Programmer. When the system is being used to program EPROMs, then the 6522,
as well as several I/O lines from the basic MICRO, is dedicated to this task.
See the section on "EPROM Programming" for details.
The addressing of the 6522 is determined by a +5 signal generated by the MEMORY
PLUS board and the AB8 and AB9 address signals. The sixteen internal registers
of the 6522 normally have the following addresses and functions:
6200 ORB Output Register B/Input Register B
6201 ORA Output Register A/Input Register A With Handshake
6202 DDRB Data Direction Register B
6203 DORA Data Direction Register A
6204 T1C-L Timer/Counter 1 Low
6205 T1C-H Timer/Counter 1 High
6206 T1L-L Timer/Counter 1 Low
6207 T1L-H Timer/Counter 1 High
6208 T2C-L Timer/Counter 2 Low
6209 T2C-H Timer/Counter 2 High
620A SR Shift Register
620B ACR Auxiliary Control Register
620C PCR Peripheral Control Register
620D IFR Interrupt Flag Register
620E IER Interrupt Enable Register
620F ORA2 Output Register A/Input Register A Without Handshake
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Last page update: 8th December, 2002. |
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