Equations

********** Mapped Logic **********
$OpTx$FX_DC$114 <= ((NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv AND
      NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND
      MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)
      OR (MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)
      OR (MyCore/Mytiming/clkcounter(1) AND
      NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)
      OR (MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)
      OR (MyCore/Mytiming/clkcounter(3) AND
      NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2));
$OpTx$FX_DC$115 <= (MyCore/hidebogus AND NOT cpuvpa AND NOT cpuvda);
$OpTx$FX_DC$119 <= ((NOT reset)
      OR (NOT cpuvpa AND NOT cpuvda));
FDCPE_MyCore/MyClock/phi0D1: FDCPE port map (MyCore/MyClock/phi0D1,NOT phi1in,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D2: FDCPE port map (MyCore/MyClock/phi0D2,MyCore/MyClock/phi0D1,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D2a: FDCPE port map (MyCore/MyClock/phi0D2a,MyCore/MyClock/phi0D2,fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D3: FDCPE port map (MyCore/MyClock/phi0D3,MyCore/MyClock/phi0D2,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D4: FDCPE port map (MyCore/MyClock/phi0D4,MyCore/MyClock/phi0D3,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D5: FDCPE port map (MyCore/MyClock/phi0D5,MyCore/MyClock/phi0D4,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D6: FDCPE port map (MyCore/MyClock/phi0D6,MyCore/MyClock/phi0D5,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D7: FDCPE port map (MyCore/MyClock/phi0D7,MyCore/MyClock/phi0D6,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D8: FDCPE port map (MyCore/MyClock/phi0D8,MyCore/MyClock/phi0D7,NOT fastclkin,'0','0');
FDCPE_MyCore/MyClock/phi0D9: FDCPE port map (MyCore/MyClock/phi0D9,MyCore/MyClock/phi0D8,MyCore/fastclkby2,'0','0');
FDCPE_MyCore/MyClock/phi0DA: FDCPE port map (MyCore/MyClock/phi0DA,MyCore/MyClock/phi0D9,MyCore/fastclkby2,'0','0');
FDCPE_MyCore/MyClock/phi0DB: FDCPE port map (MyCore/MyClock/phi0DB,MyCore/MyClock/phi0DA,MyCore/fastclkby2,'0','0');
FDCPE_MyCore/MyClock/phi0DC: FDCPE port map (MyCore/MyClock/phi0DC,MyCore/MyClock/phi0DB,MyCore/fastclkby2,'0','0');
FDCPE_MyCore/MyClock/phi0DD: FDCPE port map (MyCore/MyClock/phi0DD,MyCore/MyClock/phi0DC,MyCore/fastclkby2,'0','0');
FDCPE_MyCore/MyClockSync/slowdone: FDCPE port map (MyCore/MyClockSync/slowdone,MyCore/MyClockSync/slowdone_D,phi1in,MyCore/MyClockSync/slowdone_CLR,'0');
     MyCore/MyClockSync/slowdone_D <= ((MyCore/slowaccess AND rdy)
      OR (MyCore/MyClockSync/slowdone AND NOT rdy));
     MyCore/MyClockSync/slowdone_CLR <= (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND
      MyCore/MyClock/phi0D2a);
MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 <= (NOT cpurnw AND MyCore/ctrlsel/MyCore/ctrlsel_D2 AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2);
MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 <= (NOT cpurnw AND NOT cpuaddrin_16(0) AND
      MyCore/ctrlsel/MyCore/ctrlsel_D2);
FTCPE_MyCore/Mytiming/bydiv: FTCPE port map (MyCore/Mytiming/bydiv,MyCore/Mytiming/bydiv_T,NOT fastclkin,NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF,'0');
     MyCore/Mytiming/bydiv_T <= (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3));
MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF <= (reset AND MyCore/clkenable);
FDCPE_MyCore/Mytiming/bydivx: FDCPE port map (MyCore/Mytiming/bydivx,MyCore/Mytiming/bydiv,fastclkin,NOT reset,'0');
FDCPE_MyCore/Mytiming/clkcounter0: FDCPE port map (MyCore/Mytiming/clkcounter(0),MyCore/Mytiming/clkcounter_D(0),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(0),MyCore/Mytiming/clkcounter_PRE(0));
     MyCore/Mytiming/clkcounter_D(0) <= ((NOT MyCore/Mytiming/clkcounter(1) AND
      NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND
      NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(1) AND
      NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND
      NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(1) AND
      NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND
      MyCore/Mytiming/bydiv AND MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2)
      OR (MyCore/Mytiming/clkcounter(0) AND
      MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF));
     MyCore/Mytiming/clkcounter_CLR(0) <= (NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF);
     MyCore/Mytiming/clkcounter_PRE(0) <= (MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF);
FDCPE_MyCore/Mytiming/clkcounter1: FDCPE port map (MyCore/Mytiming/clkcounter(1),MyCore/Mytiming/clkcounter_D(1),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(1),MyCore/Mytiming/clkcounter_PRE(1));
     MyCore/Mytiming/clkcounter_D(1) <= ((NOT MyCore/Mytiming/clkcounter(0) AND
      MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND
      MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND NOT $OpTx$FX_DC$114)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND
      MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND
      NOT $OpTx$FX_DC$114));
     MyCore/Mytiming/clkcounter_CLR(1) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2);
     MyCore/Mytiming/clkcounter_PRE(1) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      NOT MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2);
FDCPE_MyCore/Mytiming/clkcounter2: FDCPE port map (MyCore/Mytiming/clkcounter(2),MyCore/Mytiming/clkcounter_D(2),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(2),MyCore/Mytiming/clkcounter_PRE(2));
     MyCore/Mytiming/clkcounter_D(2) <= ((MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (MyCore/Mytiming/clkcounter(1) AND
      NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/clkcounter(2) AND
      MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      $OpTx$FX_DC$114 AND MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2)
      OR (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND NOT $OpTx$FX_DC$114 AND
      NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2));
     MyCore/Mytiming/clkcounter_CLR(2) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2);
     MyCore/Mytiming/clkcounter_PRE(2) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2);
FTCPE_MyCore/Mytiming/clkcounter3: FTCPE port map (MyCore/Mytiming/clkcounter(3),MyCore/Mytiming/clkcounter_T(3),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(3),MyCore/Mytiming/clkcounter_PRE(3));
     MyCore/Mytiming/clkcounter_T(3) <= ((MyCore/Mytiming/clkcounter(3) AND
      NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(3) AND
      NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)
      OR (NOT MyCore/Mytiming/clkcounter(0) AND
      NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND
      MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND
      MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND
      MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 AND
      NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2));
     MyCore/Mytiming/clkcounter_CLR(3) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2);
     MyCore/Mytiming/clkcounter_PRE(3) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND
      MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2);
FDCPE_MyCore/bootrom: FDCPE port map (MyCore/bootrom,MyCore/bootrom_D,NOT MyCore/slowdetected,MyCore/bootrom_CLR,MyCore/bootrom_PRE);
     MyCore/bootrom_D <= ((MyCore/bootrom AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(6) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
     MyCore/bootrom_CLR <= (NOT reset AND NOT bootromin);
     MyCore/bootrom_PRE <= (NOT reset AND bootromin);
FDCPE_MyCore/clkenable: FDCPE port map (MyCore/clkenable,'1',MyCore/clkenable_C,MyCore/clkenable_CLR,NOT reset);
     MyCore/clkenable_C <= (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND
      MyCore/MyClock/phi0D2a);
     MyCore/clkenable_CLR <= (reset AND MyCore/slowdetected);
FDCPE_MyCore/clklatch0: FDCPE port map (MyCore/clklatch(0),MyCore/clklatch_D(0),NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/clklatch_D(0) <= ((NOT MyCore/clklatch(0) AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND cpudata(3) AND NOT cpudata(0) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND cpudata(2) AND NOT cpudata(0) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
FDCPE_MyCore/clklatch1: FDCPE port map (MyCore/clklatch(1),MyCore/clklatch_D(1),NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/clklatch_D(1) <= ((reset AND cpudata(3) AND NOT cpudata(1) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (NOT MyCore/clklatch(1) AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND cpudata(2) AND NOT cpudata(1) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
FDCPE_MyCore/clklatch2: FDCPE port map (MyCore/clklatch(2),MyCore/clklatch_D(2),NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/clklatch_D(2) <= ((NOT MyCore/clklatch(2) AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND NOT cpudata(2) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
FDCPE_MyCore/clklatch3: FDCPE port map (MyCore/clklatch(3),MyCore/clklatch_D(3),NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/clklatch_D(3) <= ((NOT MyCore/clklatch(3) AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND NOT cpudata(3) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
FDCPE_MyCore/clklatch4: FDCPE port map (MyCore/clklatch(4),MyCore/clklatch_D(4),NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/clklatch_D(4) <= ((MyCore/clklatch(4) AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND cpudata(3) AND cpudata(4) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (reset AND cpudata(2) AND cpudata(4) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(0));
MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(1));
MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 <= (NOT MyCore/useslowclk AND NOT MyCore/clklatch(2));
MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(3));
MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(4));
MyCore/ctrlsel/MyCore/ctrlsel_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND
      cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND
      cpuaddrin_2k(15) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_2k(12));
FTCPE_MyCore/fastclkby2: FTCPE port map (MyCore/fastclkby2,'1',NOT fastclkin,NOT reset,'0');
FDCPE_MyCore/fastmode: FDCPE port map (MyCore/fastmode,MyCore/fastmode_D,NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/fastmode_D <= ((MyCore/fastmode AND
      NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)
      OR (cpudata(7) AND
      MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2));
FDCPE_MyCore/fastvread: FDCPE port map (MyCore/fastvread,MyCore/fastvread_D,NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/fastvread_D <= ((MyCore/fastvread AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(2) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
FDCPE_MyCore/hidebogus: FDCPE port map (MyCore/hidebogus,MyCore/hidebogus_D,NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/hidebogus_D <= ((MyCore/hidebogus AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(3) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
MyCore/isorig/MyCore/isorig_D2 <= ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT $OpTx$FX_DC$115)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      NOT MyCore/bootrom AND MyCore/slow64k AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND
      NOT $OpTx$FX_DC$115)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND
      cpuaddrin_2k(15) AND NOT cpuaddrin_2k(12) AND NOT $OpTx$FX_DC$115)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND cpuaddrin_2k(15) AND
      NOT cpuaddrin_2k(12) AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND
      NOT $OpTx$FX_DC$115));
MyCore/isslow8/MyCore/isslow8_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpurnw AND
      NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND MyCore/fastvread AND
      cpuaddrin_2k(15) AND NOT cpuaddrin_2k(12));
FDCPE_MyCore/prgrom: FDCPE port map (MyCore/prgrom,MyCore/prgrom_D,NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/prgrom_D <= ((MyCore/prgrom AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(7) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
FDCPE_MyCore/slow64k: FDCPE port map (MyCore/slow64k,MyCore/slow64k_D,NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/slow64k_D <= ((MyCore/slow64k AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(5) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
FDCPE_MyCore/slowaccess: FDCPE port map (MyCore/slowaccess,MyCore/slowdetected,MyCore/slowaccess/MyCore/slowaccess_CLKF,MyCore/slowaccess/MyCore/slowaccess_RSTF,'0');
MyCore/slowaccess/MyCore/slowaccess_CLKF <= ((MyCore/fastmode AND phi1in AND NOT MyCore/MyClock/phi0D7)
      OR (NOT MyCore/fastmode AND phi1in AND NOT MyCore/MyClock/phi0DC));
MyCore/slowaccess/MyCore/slowaccess_RSTF <= ((NOT reset)
      OR (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND
      MyCore/MyClock/phi0D2a));
FDCPE_MyCore/slowdetected: FDCPE port map (MyCore/slowdetected,MyCore/slowdetected_D,cpuclk,NOT MyCore/slowdetected/MyCore/slowdetected_RSTF,'0');
     MyCore/slowdetected_D <= ((MyCore/useslowclk)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      MyCore/bootrom)
      OR (MyCore/isorig/MyCore/isorig_D2 AND
      NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115)
      OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND
      NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115));
MyCore/slowdetected/MyCore/slowdetected_RSTF <= (reset AND NOT MyCore/MyClockSync/slowdone);
FDCPE_MyCore/useslowclk: FDCPE port map (MyCore/useslowclk,MyCore/useslowclk_D,NOT MyCore/slowdetected,'0',NOT reset);
     MyCore/useslowclk_D <= ((MyCore/useslowclk AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(4) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
FDCPE_MyCore/wprotect0: FDCPE port map (MyCore/wprotect(0),MyCore/wprotect_D(0),NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/wprotect_D(0) <= ((MyCore/wprotect(0) AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(0) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
FDCPE_MyCore/wprotect1: FDCPE port map (MyCore/wprotect(1),MyCore/wprotect_D(1),NOT MyCore/slowdetected,NOT reset,'0');
     MyCore/wprotect_D(1) <= ((MyCore/wprotect(1) AND
      NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)
      OR (cpudata(1) AND
      MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2));
cpuclk <= NOT (((NOT MyCore/slowdetected AND NOT MyCore/Mytiming/bydiv AND
      NOT MyCore/slowaccess)
      OR (NOT MyCore/slowdetected AND NOT MyCore/slowaccess AND
      NOT MyCore/Mytiming/bydivx AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2)));
cpuwnr <= NOT cpurnw;
FDCPE_diag: FDCPE port map (diag,diag_D,NOT MyCore/slowdetected,NOT reset,'0');
     diag_D <= ((cpurnw AND MyCore/ctrlsel/MyCore/ctrlsel_D2)
      OR (diag AND NOT MyCore/ctrlsel/MyCore/ctrlsel_D2));
latchen <= NOT cpuclk;
loop1out <= '0';
loop2out <= '0';
nramcs(0) <= NOT (((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT MyCore/bootrom AND cpurnw AND cpuclk AND NOT MyCore/isorig/MyCore/isorig_D2 AND
      NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND
      NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND cpuclk AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND
      NOT cpuaddrin_2k(14) AND cpuclk AND MyCore/wprotect(1) AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND
      cpuclk AND NOT MyCore/wprotect(0) AND NOT MyCore/wprotect(1) AND
      NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND
      NOT cpuaddrin_2k(13) AND cpuclk AND MyCore/wprotect(0) AND MyCore/wprotect(1) AND
      NOT $OpTx$FX_DC$119)
      OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuclk AND
      NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      cpuaddrin_64k(18) AND cpuclk AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      cpuaddrin_64k(17) AND cpuclk AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      cpuaddrin_64k(16) AND cpuclk AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND
      cpuclk AND NOT cpuaddrin_2k(15) AND NOT $OpTx$FX_DC$119)));
nramcs(1) <= NOT ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuclk AND
      NOT $OpTx$FX_DC$119));
nromcs <= NOT (((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpurnw AND
      MyCore/slowaccess AND NOT phi1in AND NOT $OpTx$FX_DC$119)
      OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND
      MyCore/slowaccess AND NOT phi1in AND MyCore/prgrom AND NOT $OpTx$FX_DC$119)
      OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
      NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND
      NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND
      MyCore/bootrom AND cpurnw AND MyCore/slowaccess AND NOT phi1in AND
      NOT MyCore/isorig/MyCore/isorig_D2 AND NOT $OpTx$FX_DC$119)));
nromwe <= NOT ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
      cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpurnw AND
      cpuclk AND NOT $OpTx$FX_DC$119));
FDCPE_nslowbusclr: FDCPE port map (nslowbusclr,'0',nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,NOT reset,nslowbusclr_PRE);
     nslowbusclr_PRE <= (MyCore/slowdetected AND MyCore/slowaccess AND
      MyCore/isorig/MyCore/isorig_D2);
FDCPE_nslowdataenout: FDCPE port map (nslowdataenout,nslowdataenout_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,'0',MyCore/slowaccess/MyCore/slowaccess_RSTF);
     nslowdataenout_D <= (MyCore/slowdetected AND MyCore/slowaccess AND
      NOT MyCore/ctrlsel/MyCore/ctrlsel_D2 AND MyCore/isorig/MyCore/isorig_D2);
nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF <= ((MyCore/fastmode AND NOT MyCore/MyClock/phi0D2 AND
      NOT MyCore/MyClock/phi0D8)
      OR (NOT MyCore/fastmode AND NOT MyCore/MyClock/phi0D2 AND
      NOT MyCore/MyClock/phi0DD));
phi1 <= NOT phi0;
phi2 <= NOT phi1in;
FDCPE_rnw: FDCPE port map (rnw,rnw_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,'0',NOT reset);
     rnw_D <= (NOT cpurnw AND MyCore/slowdetected AND MyCore/slowaccess AND
      MyCore/isorig/MyCore/isorig_D2);
FDCPE_slowaddrlatch: FDCPE port map (slowaddrlatch,slowaddrlatch_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,slowaddrlatch_CLR,NOT reset);
     slowaddrlatch_D <= (MyCore/slowdetected AND MyCore/slowaccess AND
      MyCore/isorig/MyCore/isorig_D2);
     slowaddrlatch_CLR <= (reset AND MyCore/slowaccess/MyCore/slowaccess_RSTF);
Register Legend:
      FDCPE (Q,D,C,CLR,PRE);
      FTCPE (Q,D,C,CLR,PRE);
      LDCP (Q,D,G,CLR,PRE);