Timing Report

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Design Name PET816
Device, Speed (SpeedFile Version) XC95108, -15 (3.0)
Date Created Sat Aug 28 19:02:35 2010
Created By Timing Report Generator: version L.33
Copyright Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'MyCore/clkenable.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0D2a.Q' 'MyCore/MyClock/phi0D2.Q' 'MyCore/slowdetected.Q'.
Possible asynchronous logic: Clock pin 'MyCore/slowaccess.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0DC.Q' 'MyCore/MyClock/phi0D7.Q' 'phi1in' 'MyCore/fastmode.Q'.
Possible asynchronous logic: Clock pin 'MyCore/slowdetected.CLKF' has multiple original clock nets 'MyCore/Mytiming/bydivx.Q' 'MyCore/clklatch<0>.Q' 'MyCore/useslowclk.Q' 'MyCore/slowaccess.Q' 'MyCore/Mytiming/bydiv.Q' 'MyCore/slowdetected.Q'.
Possible asynchronous logic: Clock pin 'slowaddrlatch.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0DD.Q' 'MyCore/MyClock/phi0D8.Q' 'MyCore/MyClock/phi0D2.Q' 'MyCore/fastmode.Q'.
Possible asynchronous logic: Clock pin 'rnw.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0DD.Q' 'MyCore/MyClock/phi0D8.Q' 'MyCore/MyClock/phi0D2.Q' 'MyCore/fastmode.Q'.
Possible asynchronous logic: Clock pin 'nslowbusclr.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0DD.Q' 'MyCore/MyClock/phi0D8.Q' 'MyCore/MyClock/phi0D2.Q' 'MyCore/fastmode.Q'.
Possible asynchronous logic: Clock pin 'nslowdataenout.CLKF' has multiple original clock nets 'MyCore/MyClock/phi0DD.Q' 'MyCore/MyClock/phi0D8.Q' 'MyCore/MyClock/phi0D2.Q' 'MyCore/fastmode.Q'.

Performance Summary
Min. Clock Period 52.000 ns.
Max. Clock Frequency (fSYSTEM) 19.231 MHz.
Limited by Cycle Time for MyCore/slowdetected.Q
Clock to Setup (tCYC) 52.000 ns.
Pad to Pad Delay (tPD) 50.000 ns.
Setup to Clock at the Pad (tSU) 48.000 ns.
Clock Pad to Output Pad Delay (tCO) 150.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
AUTO_TS_F2F 0.0 54.0 101 101
AUTO_TS_P2P 0.0 150.0 73 73
AUTO_TS_P2F 0.0 62.0 387 387
AUTO_TS_F2P 0.0 57.0 47 47


Constraint: TS1000

Description: PERIOD:PERIOD_MyCore/fastclkby2.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_MyCore/MyClock/phi0D2a.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_MyCore/MyClock/phi0DC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_MyCore/MyClock/phi0D7.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_phi1in:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_MyCore/Mytiming/bydivx.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_MyCore/clklatch<0>.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_MyCore/useslowclk.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_MyCore/slowaccess.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_MyCore/Mytiming/bydiv.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_MyCore/MyClock/phi0DD.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_MyCore/MyClock/phi0D8.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_MyCore/MyClock/phi0D2.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_MyCore/fastmode.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_fastclkin:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_MyCore/slowdetected.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
MyCore/clklatch<0>.Q to MyCore/Mytiming/clkcounter<2>.D 0.000 54.000 -54.000
MyCore/clklatch<1>.Q to MyCore/Mytiming/clkcounter<2>.D 0.000 54.000 -54.000
MyCore/clklatch<2>.Q to MyCore/Mytiming/clkcounter<2>.D 0.000 54.000 -54.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
fastclkin to nramcs<0> 0.000 150.000 -150.000
fastclkin to nromcs 0.000 149.000 -149.000
phi1in to nramcs<0> 0.000 126.000 -126.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
cpuaddr_ismyio to MyCore/bootrom.D 0.000 62.000 -62.000
cpuaddr_ismyio to MyCore/fastvread.D 0.000 62.000 -62.000
cpuaddr_ismyio to MyCore/hidebogus.D 0.000 62.000 -62.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
MyCore/clklatch<0>.Q to nramcs<0> 0.000 57.000 -57.000
MyCore/fastvread.Q to nramcs<0> 0.000 57.000 -57.000
MyCore/hidebogus.Q to nramcs<0> 0.000 57.000 -57.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
MyCore/fastclkby2.Q 55.556 Limited by Cycle Time for MyCore/fastclkby2.Q
MyCore/MyClock/phi0D2a.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0D2a.Q
MyCore/MyClock/phi0DC.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0DC.Q
MyCore/MyClock/phi0D7.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0D7.Q
phi1in 55.556 Limited by Cycle Time for phi1in
MyCore/Mytiming/bydivx.Q 71.429 Limited by Clock Pulse Width for MyCore/Mytiming/bydivx.Q
MyCore/clklatch<0>.Q 71.429 Limited by Clock Pulse Width for MyCore/clklatch<0>.Q
MyCore/useslowclk.Q 71.429 Limited by Clock Pulse Width for MyCore/useslowclk.Q
MyCore/slowaccess.Q 71.429 Limited by Clock Pulse Width for MyCore/slowaccess.Q
MyCore/Mytiming/bydiv.Q 71.429 Limited by Clock Pulse Width for MyCore/Mytiming/bydiv.Q
MyCore/MyClock/phi0DD.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0DD.Q
MyCore/MyClock/phi0D8.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0D8.Q
MyCore/MyClock/phi0D2.Q 71.429 Limited by Clock Pulse Width for MyCore/MyClock/phi0D2.Q
MyCore/fastmode.Q 55.556 Limited by Cycle Time for MyCore/fastmode.Q
fastclkin 27.027 Limited by Cycle Time for fastclkin
MyCore/slowdetected.Q 19.231 Limited by Cycle Time for MyCore/slowdetected.Q

Setup/Hold Times for Clocks

Setup/Hold Times for Clock phi1in
Source Pad Setup to clk (edge) Hold to clk (edge)
rdy 4.000 0.500

Setup/Hold Times for Clock MyCore/Mytiming/bydivx.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/clklatch<0>.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddrin_2k<11> -20.000 24.500
cpuaddrin_2k<12> -3.000 7.500
cpuaddrin_2k<13> -3.000 7.500
cpuaddrin_2k<14> -3.000 7.500
cpuaddrin_2k<15> -3.000 7.500
cpuaddrin_64k<16> -3.000 7.500
cpuaddrin_64k<17> -3.000 7.500
cpuaddrin_64k<18> -3.000 7.500
cpuaddrin_64k<19> -3.000 7.500
cpuaddrin_64k<20> -3.000 7.500
cpuaddrin_64k<21> -3.000 7.500
cpuaddrin_64k<22> -3.000 7.500
cpuaddrin_64k<23> -3.000 7.500
cpurnw -3.000 7.500
cpuvda -3.000 7.500
cpuvpa -3.000 7.500

Setup/Hold Times for Clock MyCore/useslowclk.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddrin_2k<11> -20.000 24.500
cpuaddrin_2k<12> -3.000 7.500
cpuaddrin_2k<13> -3.000 7.500
cpuaddrin_2k<14> -3.000 7.500
cpuaddrin_2k<15> -3.000 7.500
cpuaddrin_64k<16> -3.000 7.500
cpuaddrin_64k<17> -3.000 7.500
cpuaddrin_64k<18> -3.000 7.500
cpuaddrin_64k<19> -3.000 7.500
cpuaddrin_64k<20> -3.000 7.500
cpuaddrin_64k<21> -3.000 7.500
cpuaddrin_64k<22> -3.000 7.500
cpuaddrin_64k<23> -3.000 7.500
cpurnw -3.000 7.500
cpuvda -3.000 7.500
cpuvpa -3.000 7.500

Setup/Hold Times for Clock MyCore/slowaccess.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/Mytiming/bydiv.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/MyClock/phi0DD.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddr_ismyio -3.000 7.500
cpuaddrin_16<1> -3.000 7.500
cpuaddrin_16<2> -3.000 7.500
cpuaddrin_16<3> -3.000 7.500
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/MyClock/phi0D8.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddr_ismyio -3.000 7.500
cpuaddrin_16<1> -3.000 7.500
cpuaddrin_16<2> -3.000 7.500
cpuaddrin_16<3> -3.000 7.500
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/MyClock/phi0D2.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddr_ismyio -3.000 7.500
cpuaddrin_16<1> -3.000 7.500
cpuaddrin_16<2> -3.000 7.500
cpuaddrin_16<3> -3.000 7.500
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock MyCore/fastmode.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddr_ismyio -3.000 7.500
cpuaddrin_16<1> -3.000 7.500
cpuaddrin_16<2> -3.000 7.500
cpuaddrin_16<3> -3.000 7.500
cpuaddrin_2k<11> -3.000 7.500
cpuaddrin_2k<12> 14.000 0.000
cpuaddrin_2k<13> 14.000 0.000
cpuaddrin_2k<14> 14.000 0.000
cpuaddrin_2k<15> 14.000 0.000
cpuaddrin_64k<16> 14.000 0.000
cpuaddrin_64k<17> 14.000 0.000
cpuaddrin_64k<18> 14.000 0.000
cpuaddrin_64k<19> 14.000 0.000
cpuaddrin_64k<20> 14.000 0.000
cpuaddrin_64k<21> 14.000 0.000
cpuaddrin_64k<22> 14.000 0.000
cpuaddrin_64k<23> 14.000 0.000
cpurnw 14.000 0.000
cpuvda 14.000 0.000
cpuvpa 14.000 0.000

Setup/Hold Times for Clock fastclkin
Source Pad Setup to clk (edge) Hold to clk (edge)
phi1in 8.000 0.000
reset 26.000 0.000

Setup/Hold Times for Clock MyCore/slowdetected.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
cpuaddr_ismyio 48.000 0.000
cpuaddrin_16<0> 31.000 0.000
cpuaddrin_16<1> 48.000 0.000
cpuaddrin_16<2> 48.000 0.000
cpuaddrin_16<3> 48.000 0.000
cpuaddrin_2k<11> 48.000 7.500
cpuaddrin_2k<12> 48.000 0.000
cpuaddrin_2k<13> 48.000 0.000
cpuaddrin_2k<14> 48.000 0.000
cpuaddrin_2k<15> 48.000 0.000
cpuaddrin_64k<16> 48.000 0.000
cpuaddrin_64k<17> 48.000 0.000
cpuaddrin_64k<18> 48.000 0.000
cpuaddrin_64k<19> 48.000 0.000
cpuaddrin_64k<20> 48.000 0.000
cpuaddrin_64k<21> 48.000 0.000
cpuaddrin_64k<22> 48.000 0.000
cpuaddrin_64k<23> 48.000 0.000
cpudata<0> -3.000 7.500
cpudata<1> -2.000 7.500
cpudata<2> -3.000 7.500
cpudata<3> -2.000 7.500
cpudata<4> -3.000 7.500
cpudata<5> -3.000 7.500
cpudata<6> -3.000 7.500
cpudata<7> -3.000 7.500
cpurnw 31.000 7.500
cpuvda 14.000 0.000
cpuvpa 14.000 0.000
reset -2.000 7.500


Clock to Pad Timing

Clock phi1in to Pad
Destination Pad Clock (edge) to Pad
nramcs<0> 126.000
nromcs 125.000
latchen 94.000
nramcs<1> 94.000
nromwe 94.000
cpuclk 77.000
diag 74.000

Clock fastclkin to Pad
Destination Pad Clock (edge) to Pad
nramcs<0> 150.000
nromcs 149.000
latchen 118.000
nramcs<1> 118.000
nromwe 118.000
cpuclk 101.000
diag 98.000
nslowbusclr 53.000
nslowdataenout 53.000
rnw 53.000
slowaddrlatch 53.000


Clock to Setup Times for Clocks

Clock to Setup for clock MyCore/fastclkby2.Q
Source Destination Delay
MyCore/MyClock/phi0D9.Q MyCore/MyClock/phi0DA.D 18.000
MyCore/MyClock/phi0DA.Q MyCore/MyClock/phi0DB.D 18.000
MyCore/MyClock/phi0DB.Q MyCore/MyClock/phi0DC.D 18.000
MyCore/MyClock/phi0DC.Q MyCore/MyClock/phi0DD.D 18.000

Clock to Setup for clock phi1in
Source Destination Delay
MyCore/MyClockSync/slowdone.Q MyCore/MyClockSync/slowdone.D 18.000
MyCore/slowaccess.Q MyCore/MyClockSync/slowdone.D 18.000

Clock to Setup for clock MyCore/fastmode.Q
Source Destination Delay
MyCore/slowaccess.Q nslowdataenout.D 18.000
MyCore/slowaccess.Q rnw.D 18.000
MyCore/slowaccess.Q slowaddrlatch.D 18.000

Clock to Setup for clock fastclkin
Source Destination Delay
MyCore/Mytiming/bydiv.Q MyCore/Mytiming/clkcounter<2>.D 37.000
MyCore/Mytiming/clkcounter<0>.Q MyCore/Mytiming/clkcounter<2>.D 37.000
MyCore/Mytiming/clkcounter<1>.Q MyCore/Mytiming/clkcounter<2>.D 37.000
MyCore/Mytiming/clkcounter<2>.Q MyCore/Mytiming/clkcounter<2>.D 37.000
MyCore/Mytiming/clkcounter<3>.Q MyCore/Mytiming/clkcounter<2>.D 37.000
MyCore/Mytiming/bydiv.Q MyCore/Mytiming/clkcounter<1>.D 36.000
MyCore/Mytiming/clkcounter<0>.Q MyCore/Mytiming/clkcounter<1>.D 36.000
MyCore/Mytiming/clkcounter<1>.Q MyCore/Mytiming/clkcounter<1>.D 36.000
MyCore/Mytiming/clkcounter<2>.Q MyCore/Mytiming/clkcounter<1>.D 36.000
MyCore/Mytiming/clkcounter<3>.Q MyCore/Mytiming/clkcounter<1>.D 36.000
MyCore/Mytiming/bydiv.Q MyCore/Mytiming/clkcounter<0>.D 19.000
MyCore/Mytiming/bydiv.Q MyCore/Mytiming/clkcounter<3>.D 19.000
MyCore/Mytiming/clkcounter<0>.Q MyCore/Mytiming/clkcounter<3>.D 19.000
MyCore/Mytiming/clkcounter<1>.Q MyCore/Mytiming/clkcounter<0>.D 19.000
MyCore/Mytiming/clkcounter<1>.Q MyCore/Mytiming/clkcounter<3>.D 19.000
MyCore/Mytiming/clkcounter<2>.Q MyCore/Mytiming/clkcounter<0>.D 19.000
MyCore/Mytiming/clkcounter<2>.Q MyCore/Mytiming/clkcounter<3>.D 19.000
MyCore/Mytiming/clkcounter<3>.Q MyCore/Mytiming/clkcounter<0>.D 19.000
MyCore/Mytiming/clkcounter<3>.Q MyCore/Mytiming/clkcounter<3>.D 19.000
MyCore/MyClock/phi0D1.Q MyCore/MyClock/phi0D2.D 18.000
MyCore/MyClock/phi0D2.Q MyCore/MyClock/phi0D2a.D 18.000
MyCore/MyClock/phi0D2.Q MyCore/MyClock/phi0D3.D 18.000
MyCore/MyClock/phi0D3.Q MyCore/MyClock/phi0D4.D 18.000
MyCore/MyClock/phi0D4.Q MyCore/MyClock/phi0D5.D 18.000
MyCore/MyClock/phi0D5.Q MyCore/MyClock/phi0D6.D 18.000
MyCore/MyClock/phi0D6.Q MyCore/MyClock/phi0D7.D 18.000
MyCore/MyClock/phi0D7.Q MyCore/MyClock/phi0D8.D 18.000
MyCore/Mytiming/bydiv.Q MyCore/Mytiming/bydivx.D 18.000
MyCore/Mytiming/clkcounter<0>.Q MyCore/Mytiming/bydiv.D 18.000
MyCore/Mytiming/clkcounter<0>.Q MyCore/Mytiming/clkcounter<0>.D 18.000
MyCore/Mytiming/clkcounter<1>.Q MyCore/Mytiming/bydiv.D 18.000
MyCore/Mytiming/clkcounter<2>.Q MyCore/Mytiming/bydiv.D 18.000
MyCore/Mytiming/clkcounter<3>.Q MyCore/Mytiming/bydiv.D 18.000

Clock to Setup for clock MyCore/slowdetected.Q
Source Destination Delay
MyCore/fastvread.Q MyCore/slowdetected.D 52.000
MyCore/hidebogus.Q MyCore/slowdetected.D 52.000
MyCore/bootrom.Q MyCore/slowdetected.D 35.000
MyCore/slow64k.Q MyCore/slowdetected.D 35.000
MyCore/bootrom.Q MyCore/bootrom.D 18.000
MyCore/clklatch<0>.Q MyCore/clklatch<0>.D 18.000
MyCore/clklatch<1>.Q MyCore/clklatch<1>.D 18.000
MyCore/clklatch<2>.Q MyCore/clklatch<2>.D 18.000
MyCore/clklatch<3>.Q MyCore/clklatch<3>.D 18.000
MyCore/clklatch<4>.Q MyCore/clklatch<4>.D 18.000
MyCore/fastmode.Q MyCore/fastmode.D 18.000
MyCore/fastvread.Q MyCore/fastvread.D 18.000
MyCore/hidebogus.Q MyCore/hidebogus.D 18.000
MyCore/prgrom.Q MyCore/prgrom.D 18.000
MyCore/slow64k.Q MyCore/slow64k.D 18.000
MyCore/useslowclk.Q MyCore/slowdetected.D 18.000
MyCore/useslowclk.Q MyCore/useslowclk.D 18.000
MyCore/wprotect<0>.Q MyCore/wprotect<0>.D 18.000
MyCore/wprotect<1>.Q MyCore/wprotect<1>.D 18.000
diag.Q diag.D 18.000


Pad to Pad List

Source Pad Destination Pad Delay
cpuaddrin_2k<12> nramcs<0> 50.000
cpuaddrin_2k<13> nramcs<0> 50.000
cpuaddrin_2k<14> nramcs<0> 50.000
cpuaddrin_2k<15> nramcs<0> 50.000
cpuaddrin_64k<16> nramcs<0> 50.000
cpuaddrin_64k<17> nramcs<0> 50.000
cpuaddrin_64k<18> nramcs<0> 50.000
cpuaddrin_64k<19> nramcs<0> 50.000
cpuaddrin_64k<20> nramcs<0> 50.000
cpuaddrin_64k<21> nramcs<0> 50.000
cpuaddrin_64k<22> nramcs<0> 50.000
cpuaddrin_64k<23> nramcs<0> 50.000
cpurnw nramcs<0> 50.000
cpuvda nramcs<0> 50.000
cpuvpa nramcs<0> 50.000
cpuaddrin_2k<12> nromcs 49.000
cpuaddrin_2k<13> nromcs 49.000
cpuaddrin_2k<14> nromcs 49.000
cpuaddrin_2k<15> nromcs 49.000
cpuaddrin_64k<16> nromcs 49.000
cpuaddrin_64k<17> nromcs 49.000
cpuaddrin_64k<18> nromcs 49.000
cpuaddrin_64k<19> nromcs 49.000
cpuaddrin_64k<20> nromcs 49.000
cpuaddrin_64k<21> nromcs 49.000
cpuaddrin_64k<22> nromcs 49.000
cpuaddrin_64k<23> nromcs 49.000
cpurnw nromcs 49.000
cpuvda nromcs 49.000
cpuvpa nromcs 49.000
cpuaddrin_2k<11> nramcs<0> 33.000
reset nramcs<0> 33.000
cpuaddrin_2k<11> nromcs 32.000
cpuvda nramcs<1> 32.000
cpuvda nromwe 32.000
cpuvpa nramcs<1> 32.000
cpuvpa nromwe 32.000
reset nramcs<1> 32.000
reset nromcs 32.000
reset nromwe 32.000
cpuaddrin_64k<19> nramcs<1> 15.000
cpuaddrin_64k<19> nromwe 15.000
cpuaddrin_64k<20> nramcs<1> 15.000
cpuaddrin_64k<20> nromwe 15.000
cpuaddrin_64k<21> nramcs<1> 15.000
cpuaddrin_64k<21> nromwe 15.000
cpuaddrin_64k<22> nramcs<1> 15.000
cpuaddrin_64k<22> nromwe 15.000
cpuaddrin_64k<23> nramcs<1> 15.000
cpuaddrin_64k<23> nromwe 15.000
cpurnw cpuwnr 15.000
cpurnw nromwe 15.000
phi0 phi1 15.000
phi1in nromcs 15.000
phi1in phi2 15.000



Number of paths analyzed: 608
Number of Timing errors: 608
Analysis Completed: Sat Aug 28 19:02:35 2010