FB1
FB2
FB3
FB4
FB5
FB6
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
MyCore/Mytiming/clkcounter<3>
11
18_5
1_1
1_2
1_3
1_4
1_5
2_1
2_2
2_3
2_4
2_5
MC1
STD
(b)
(b)
(unused)
0
MC2
1
I/O
I
(unused)
0
MC3
2
I/O
I
MyCore/slowaccess/MyCore/slowaccess_RSTF
2
4_1
4_2
MC4
STD
(b)
(b)
MyCore/Mytiming/bydivx
2
5_1
5_2
MC5
STD
3
I/O
I
MyCore/Mytiming/bydiv
2
6_1
6_2
MC6
STD
4
I/O
I
MyCore/slowaccess
3
7_1
7_2
7_3
MC7
STD
(b)
(b)
MyCore/clkenable
3
8_1
8_2
8_3
MC8
STD
5
I/O
I
cpuclk
2
9_1
9_2
MC9
STD
6
I/O
O
MyCore/MyClockSync/slowdone
4
10_1
10_2
10_3
10_4
MC10
STD
(b)
(b)
nslowdataenout
3
11_1
11_2
11_3
MC11
STD
7
I/O
O
MyCore/clklatch<1>
5
11_4
12_1
12_2
12_3
12_4
MC12
STD
9
I/O/GCK1
I
$OpTx$FX_DC$114
5
12_5
13_1
13_2
13_3
13_4
MC13
STD
(b)
(b)
MyCore/Mytiming/clkcounter<1>
7
13_5
14_1
14_1
14_2
14_3
14_5
15_5
MC14
STD
10
I/O/GCK2
GCK
MyCore/Mytiming/clkcounter<0>
7
15_1
15_2
15_2
15_4
16_2
16_3
16_4
MC15
STD
11
I/O
I
phi2
1
16_1
MC16
STD
12
I/O/GCK3
O
MyCore/slowdetected/MyCore/slowdetected_RSTF
1
17_1
MC17
STD
13
I/O
I
MyCore/Mytiming/clkcounter<2>
8
17_2
17_3
17_4
17_5
18_1
18_1
18_2
18_4
MC18
STD
(b)
(b)
Signals Used By Logic in Function Block
$OpTx$FX_DC$114
MyCore/MyClock/phi0D2
MyCore/MyClock/phi0D2a
MyCore/MyClockSync/slowdone
MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2
MyCore/Mytiming/bydiv
MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF
MyCore/Mytiming/bydivx
MyCore/Mytiming/clkcounter<0>
MyCore/Mytiming/clkcounter<1>
MyCore/Mytiming/clkcounter<2>
MyCore/Mytiming/clkcounter<3>
MyCore/clklatch<1>
MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2
MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2
MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2
MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2
MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2
MyCore/ctrlsel/MyCore/ctrlsel_D2
MyCore/isorig/MyCore/isorig_D2
MyCore/slowaccess
MyCore/slowaccess/MyCore/slowaccess_CLKF
MyCore/slowaccess/MyCore/slowaccess_RSTF
MyCore/slowdetected
cpudata<1>
cpudata<2>
cpudata<3>
nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF
phi1in
rdy
reset