cpldfit: version L.33 Xilinx Inc. Fitter Report Design Name: PET816 Date: 8-28-2010, 7:02PM Device Used: XC95108-15-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 73 /108 ( 68%) 200 /540 ( 37%) 160/216 ( 74%) 44 /108 ( 41%) 51 /69 ( 74%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 16/18 31/36 31 66/90 3/12 FB2 16/18 31/36 31 24/90 1/12 FB3 16/18 32/36 32 45/90 3/12 FB4 2/18 2/36 2 2/90 0/11 FB5 8/18 32/36 32 23/90 5/11 FB6 15/18 32/36 32 40/90 4/11 ----- ----- ----- ----- 73/108 160/216 200/540 16/69 * - Resource is exhausted ** Global Control Resources ** The complement of 'fastclkin' mapped onto global clock net GCK1. Signal 'fastclkin' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 34 34 | I/O : 48 63 Output : 16 16 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 1 1 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 51 51 ** Power Data ** There are 73 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'fastclkin' based upon the LOC constraint 'P10'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'phi0' based upon the LOC constraint 'P9'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'auxconf'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'loop1in'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'loop2in'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'phi0_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. ************************* Summary of Mapped Logic ************************ ** 16 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State cpuclk 2 5 FB1_9 6 I/O O STD FAST nslowdataenout 3 6 FB1_11 7 I/O O STD FAST RESET phi2 1 1 FB1_16 12 GCK/I/O O STD FAST cpuwnr 1 1 FB2_11 79 I/O O STD FAST slowaddrlatch 4 6 FB3_9 20 I/O O STD FAST RESET phi1 1 1 FB3_12 23 I/O O STD FAST loop2out 0 0 FB3_17 31 I/O O STD FAST nslowbusclr 3 5 FB5_2 32 I/O O STD FAST RESET rnw 3 6 FB5_3 33 I/O O STD FAST RESET loop1out 0 0 FB5_5 34 I/O O STD FAST nramcs<0> 10 18 FB5_14 41 I/O O STD FAST nramcs<1> 1 7 FB5_15 43 I/O O STD FAST nromwe 1 8 FB6_8 50 I/O O STD FAST diag 4 5 FB6_9 51 I/O O STD FAST RESET latchen 1 1 FB6_11 52 I/O O STD FAST nromcs 3 15 FB6_12 53 I/O O STD FAST ** 57 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State MyCore/Mytiming/clkcounter<3> 11 11 FB1_1 STD SET MyCore/slowaccess/MyCore/slowaccess_RSTF 2 4 FB1_4 STD MyCore/Mytiming/bydivx 2 2 FB1_5 STD RESET MyCore/Mytiming/bydiv 2 5 FB1_6 STD RESET MyCore/slowaccess 3 3 FB1_7 STD RESET MyCore/clkenable 3 4 FB1_8 STD RESET MyCore/MyClockSync/slowdone 4 7 FB1_10 STD RESET MyCore/clklatch<1> 5 7 FB1_12 STD RESET $OpTx$FX_DC$114 5 8 FB1_13 STD MyCore/Mytiming/clkcounter<1> 7 10 FB1_14 STD SET MyCore/Mytiming/clkcounter<0> 7 8 FB1_15 STD SET MyCore/slowdetected/MyCore/slowdetected_RSTF 1 2 FB1_17 STD MyCore/Mytiming/clkcounter<2> 8 7 FB1_18 STD SET MyCore/fastclkby2 1 1 FB2_3 STD RESET MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2 1 2 FB2_4 STD MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF 1 2 FB2_5 STD MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 1 3 FB2_6 STD MyCore/MyClock/phi0D6 1 1 FB2_7 STD RESET MyCore/MyClock/phi0D5 1 1 FB2_8 STD RESET MyCore/MyClock/phi0D4 1 1 FB2_9 STD RESET MyCore/MyClock/phi0D3 1 1 FB2_10 STD RESET MyCore/MyClock/phi0D2a 1 1 FB2_12 STD RESET MyCore/MyClock/phi0D2 1 1 FB2_13 STD RESET MyCore/MyClock/phi0D1 1 1 FB2_14 STD RESET MyCore/MyClock/phi0DC 2 2 FB2_15 STD RESET MyCore/MyClock/phi0DB 2 2 FB2_16 STD RESET MyCore/MyClock/phi0DA 2 2 FB2_17 STD RESET MyCore/slowdetected 6 15 FB2_18 STD RESET $OpTx$FX_DC$115 1 3 FB3_3 STD nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 2 4 FB3_4 STD MyCore/slowaccess/MyCore/slowaccess_CLKF 2 4 FB3_5 STD MyCore/MyClock/phi0DD 2 2 FB3_6 STD RESET MyCore/MyClock/phi0D9 2 2 FB3_7 STD RESET $OpTx$FX_DC$119 2 3 FB3_8 STD MyCore/wprotect<1> 4 5 FB3_10 STD RESET MyCore/wprotect<0> 4 5 FB3_11 STD RESET MyCore/slow64k 4 5 FB3_13 STD RESET MyCore/prgrom 4 5 FB3_14 STD RESET MyCore/hidebogus 4 5 FB3_15 STD RESET MyCore/fastmode 4 5 FB3_16 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State MyCore/bootrom 5 6 FB3_18 STD RESET MyCore/MyClock/phi0D8 1 1 FB4_17 STD RESET MyCore/MyClock/phi0D7 1 1 FB4_18 STD RESET MyCore/isslow8/MyCore/isslow8_D2 1 14 FB5_16 STD MyCore/ctrlsel/MyCore/ctrlsel_D2 1 17 FB5_17 STD MyCore/isorig/MyCore/isorig_D2 4 17 FB5_18 STD MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2 1 2 FB6_4 STD MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2 1 2 FB6_5 STD MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2 1 2 FB6_6 STD MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2 1 2 FB6_7 STD MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 1 3 FB6_10 STD MyCore/useslowclk 4 5 FB6_13 STD RESET MyCore/fastvread 4 5 FB6_14 STD RESET MyCore/clklatch<3> 4 5 FB6_15 STD RESET MyCore/clklatch<2> 4 5 FB6_16 STD RESET MyCore/clklatch<4> 5 7 FB6_17 STD RESET MyCore/clklatch<0> 5 7 FB6_18 STD RESET ** 35 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use cpuaddrin_2k<12> FB1_2 1 I/O I cpuaddrin_2k<13> FB1_3 2 I/O I cpuaddrin_2k<14> FB1_5 3 I/O I cpuaddrin_2k<15> FB1_6 4 I/O I cpuaddrin_2k<11> FB1_8 5 I/O I phi0 FB1_12 9 GCK/I/O I fastclkin FB1_14 10 GCK/I/O GCK cpuvpa FB1_15 11 I/O I cpuvda FB1_17 13 I/O I cpuaddrin_64k<16> FB2_2 71 I/O I cpuaddrin_64k<17> FB2_3 72 I/O I cpuaddrin_64k<18> FB2_6 75 I/O I cpuaddrin_16<1> FB2_14 81 I/O I cpuaddrin_16<0> FB2_15 82 I/O I cpuaddrin_16<3> FB2_16 83 I/O I cpuaddrin_16<2> FB2_17 84 I/O I cpurnw FB3_5 17 I/O I reset FB3_6 18 I/O I bootromin FB3_8 19 I/O I cpuaddr_ismyio FB3_15 25 I/O I cpudata<2> FB4_2 57 I/O I cpudata<4> FB4_3 58 I/O I cpudata<6> FB4_5 61 I/O I cpudata<7> FB4_6 62 I/O I cpudata<5> FB4_8 63 I/O I cpuaddrin_64k<23> FB4_11 66 I/O I cpuaddrin_64k<22> FB4_12 67 I/O I cpuaddrin_64k<21> FB4_14 68 I/O I cpuaddrin_64k<20> FB4_15 69 I/O I cpuaddrin_64k<19> FB4_17 70 I/O I rdy FB5_11 39 I/O I phi1in FB5_17 44 I/O I cpudata<1> FB6_14 54 I/O I cpudata<0> FB6_15 55 I/O I cpudata<3> FB6_17 56 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use MyCore/Mytiming/clkcounter<3> 11 6<- 0 0 FB1_1 (b) (b) (unused) 0 0 /\5 0 FB1_2 1 I/O I (unused) 0 0 0 5 FB1_3 2 I/O I MyCore/slowaccess/MyCore/slowaccess_RSTF 2 0 0 3 FB1_4 (b) (b) MyCore/Mytiming/bydivx 2 0 0 3 FB1_5 3 I/O I MyCore/Mytiming/bydiv 2 0 0 3 FB1_6 4 I/O I MyCore/slowaccess 3 0 0 2 FB1_7 (b) (b) MyCore/clkenable 3 0 0 2 FB1_8 5 I/O I cpuclk 2 0 0 3 FB1_9 6 I/O O MyCore/MyClockSync/slowdone 4 0 0 1 FB1_10 (b) (b) nslowdataenout 3 0 \/1 1 FB1_11 7 I/O O MyCore/clklatch<1> 5 1<- \/1 0 FB1_12 9 GCK/I/O I $OpTx$FX_DC$114 5 1<- \/1 0 FB1_13 (b) (b) MyCore/Mytiming/clkcounter<1> 7 2<- 0 0 FB1_14 10 GCK/I/O GCK MyCore/Mytiming/clkcounter<0> 7 3<- /\1 0 FB1_15 11 I/O I phi2 1 0 /\3 1 FB1_16 12 GCK/I/O O MyCore/slowdetected/MyCore/slowdetected_RSTF 1 0 \/4 0 FB1_17 13 I/O I MyCore/Mytiming/clkcounter<2> 8 4<- \/1 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$114 12: MyCore/Mytiming/clkcounter<3> 22: MyCore/slowaccess/MyCore/slowaccess_CLKF 2: MyCore/MyClock/phi0D2 13: MyCore/clklatch<1> 23: MyCore/slowaccess/MyCore/slowaccess_RSTF 3: MyCore/MyClock/phi0D2a 14: MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2 24: MyCore/slowdetected 4: MyCore/MyClockSync/slowdone 15: MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2 25: cpudata<1> 5: MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 16: MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2 26: cpudata<2> 6: MyCore/Mytiming/bydiv 17: MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2 27: cpudata<3> 7: MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF 18: MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2 28: nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 8: MyCore/Mytiming/bydivx 19: MyCore/ctrlsel/MyCore/ctrlsel_D2 29: phi1in 9: MyCore/Mytiming/clkcounter<0> 20: MyCore/isorig/MyCore/isorig_D2 30: rdy 10: MyCore/Mytiming/clkcounter<1> 21: MyCore/slowaccess 31: reset 11: MyCore/Mytiming/clkcounter<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyCore/Mytiming/clkcounter<3> .....XX.XXXX.XXXXX...................... 11 11 MyCore/slowaccess/MyCore/slowaccess_RSTF .XX....................X......X......... 4 4 MyCore/Mytiming/bydivx .....X........................X......... 2 2 MyCore/Mytiming/bydiv ......X.XXXX............................ 5 5 MyCore/slowaccess .....................XXX................ 3 3 MyCore/clkenable .XX....................X......X......... 4 4 cpuclk .....X.X.....X......X..X................ 5 5 MyCore/MyClockSync/slowdone .XXX................X..X....XX.......... 7 7 nslowdataenout ..................XXX.XX...X............ 6 6 MyCore/clklatch<1> ....X.......X..........XXXX...X......... 7 7 $OpTx$FX_DC$114 .....X..XXXX.XXX........................ 8 8 MyCore/Mytiming/clkcounter<1> X....XX.XXXX.XXX........................ 10 10 MyCore/Mytiming/clkcounter<0> .....XX.XXXX.XX......................... 8 8 phi2 ............................X........... 1 1 MyCore/slowdetected/MyCore/slowdetected_RSTF ...X..........................X......... 2 2 MyCore/Mytiming/clkcounter<2> X.....X.XXXX....X....................... 7 7 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 71 I/O I MyCore/fastclkby2 1 0 0 4 FB2_3 72 I/O I MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2 1 0 0 4 FB2_4 (b) (b) MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF 1 0 0 4 FB2_5 74 GSR/I/O (b) MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 1 0 0 4 FB2_6 75 I/O I MyCore/MyClock/phi0D6 1 0 0 4 FB2_7 (b) (b) MyCore/MyClock/phi0D5 1 0 0 4 FB2_8 76 GTS/I/O (b) MyCore/MyClock/phi0D4 1 0 0 4 FB2_9 77 GTS/I/O (b) MyCore/MyClock/phi0D3 1 0 0 4 FB2_10 (b) (b) cpuwnr 1 0 0 4 FB2_11 79 I/O O MyCore/MyClock/phi0D2a 1 0 0 4 FB2_12 80 I/O (b) MyCore/MyClock/phi0D2 1 0 0 4 FB2_13 (b) (b) MyCore/MyClock/phi0D1 1 0 0 4 FB2_14 81 I/O I MyCore/MyClock/phi0DC 2 0 0 3 FB2_15 82 I/O I MyCore/MyClock/phi0DB 2 0 0 3 FB2_16 83 I/O I MyCore/MyClock/phi0DA 2 0 \/1 2 FB2_17 84 I/O I MyCore/slowdetected 6 1<- 0 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$115 12: MyCore/clklatch<1> 22: cpuaddrin_64k<18> 2: MyCore/MyClock/phi0D1 13: MyCore/ctrlsel/MyCore/ctrlsel_D2 23: cpuaddrin_64k<19> 3: MyCore/MyClock/phi0D2 14: MyCore/fastclkby2 24: cpuaddrin_64k<20> 4: MyCore/MyClock/phi0D3 15: MyCore/isorig/MyCore/isorig_D2 25: cpuaddrin_64k<21> 5: MyCore/MyClock/phi0D4 16: MyCore/isslow8/MyCore/isslow8_D2 26: cpuaddrin_64k<22> 6: MyCore/MyClock/phi0D5 17: MyCore/slowdetected/MyCore/slowdetected_RSTF 27: cpuaddrin_64k<23> 7: MyCore/MyClock/phi0D9 18: MyCore/useslowclk 28: cpuclk 8: MyCore/MyClock/phi0DA 19: cpuaddrin_16<0> 29: cpurnw 9: MyCore/MyClock/phi0DB 20: cpuaddrin_64k<16> 30: phi1in 10: MyCore/bootrom 21: cpuaddrin_64k<17> 31: reset 11: MyCore/clkenable Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyCore/fastclkby2 ..............................X......... 1 1 MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2 ...........X.....X...................... 2 2 MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF ..........X...................X......... 2 2 MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 ............X.....X.........X........... 3 3 MyCore/MyClock/phi0D6 .....X.................................. 1 1 MyCore/MyClock/phi0D5 ....X................................... 1 1 MyCore/MyClock/phi0D4 ...X.................................... 1 1 MyCore/MyClock/phi0D3 ..X..................................... 1 1 cpuwnr ............................X........... 1 1 MyCore/MyClock/phi0D2a ..X..................................... 1 1 MyCore/MyClock/phi0D2 .X...................................... 1 1 MyCore/MyClock/phi0D1 .............................X.......... 1 1 MyCore/MyClock/phi0DC ........X....X.......................... 2 2 MyCore/MyClock/phi0DB .......X.....X.......................... 2 2 MyCore/MyClock/phi0DA ......X......X.......................... 2 2 MyCore/slowdetected X........X....XXXX.XXXXXXXXX............ 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O $OpTx$FX_DC$115 1 0 0 4 FB3_3 15 I/O (b) nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 2 0 0 3 FB3_4 (b) (b) MyCore/slowaccess/MyCore/slowaccess_CLKF 2 0 0 3 FB3_5 17 I/O I MyCore/MyClock/phi0DD 2 0 0 3 FB3_6 18 I/O I MyCore/MyClock/phi0D9 2 0 0 3 FB3_7 (b) (b) $OpTx$FX_DC$119 2 0 0 3 FB3_8 19 I/O I slowaddrlatch 4 0 0 1 FB3_9 20 I/O O MyCore/wprotect<1> 4 0 0 1 FB3_10 (b) (b) MyCore/wprotect<0> 4 0 0 1 FB3_11 21 I/O (b) phi1 1 0 0 4 FB3_12 23 I/O O MyCore/slow64k 4 0 0 1 FB3_13 (b) (b) MyCore/prgrom 4 0 0 1 FB3_14 24 I/O (b) MyCore/hidebogus 4 0 0 1 FB3_15 25 I/O I MyCore/fastmode 4 0 0 1 FB3_16 26 I/O (b) loop2out 0 0 0 5 FB3_17 31 I/O O MyCore/bootrom 5 0 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: MyCore/MyClock/phi0D2 12: MyCore/isorig/MyCore/isorig_D2 23: cpudata<3> 2: MyCore/MyClock/phi0D7 13: MyCore/prgrom 24: cpudata<5> 3: MyCore/MyClock/phi0D8 14: MyCore/slow64k 25: cpudata<6> 4: MyCore/MyClock/phi0DC 15: MyCore/slowaccess 26: cpudata<7> 5: MyCore/MyClock/phi0DD 16: MyCore/slowaccess/MyCore/slowaccess_RSTF 27: cpuvda 6: MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 17: MyCore/slowdetected 28: cpuvpa 7: MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 18: MyCore/wprotect<0> 29: nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 8: MyCore/bootrom 19: MyCore/wprotect<1> 30: phi0 9: MyCore/fastclkby2 20: bootromin 31: phi1in 10: MyCore/fastmode 21: cpudata<0> 32: reset 11: MyCore/hidebogus 22: cpudata<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs $OpTx$FX_DC$115 ..........X...............XX............ 3 3 nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF X.X.X....X.............................. 4 4 MyCore/slowaccess/MyCore/slowaccess_CLKF .X.X.....X....................X......... 4 4 MyCore/MyClock/phi0DD ...X....X............................... 2 2 MyCore/MyClock/phi0D9 ..X.....X............................... 2 2 $OpTx$FX_DC$119 ..........................XX...X........ 3 3 slowaddrlatch ...........X..XXX...........X..X........ 6 6 MyCore/wprotect<1> .....X..........X.X..X.........X........ 5 5 MyCore/wprotect<0> .....X..........XX..X..........X........ 5 5 phi1 .............................X.......... 1 1 MyCore/slow64k .....X.......X..X......X.......X........ 5 5 MyCore/prgrom .....X......X...X........X.....X........ 5 5 MyCore/hidebogus .....X....X.....X.....X........X........ 5 5 MyCore/fastmode ......X..X......X........X.....X........ 5 5 loop2out ........................................ 0 0 MyCore/bootrom .....X.X........X..X....X......X........ 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 2/34 Number of signals used by logic mapping into function block: 2 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 57 I/O I (unused) 0 0 0 5 FB4_3 58 I/O I (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 61 I/O I (unused) 0 0 0 5 FB4_6 62 I/O I (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 63 I/O I (unused) 0 0 0 5 FB4_9 65 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 66 I/O I (unused) 0 0 0 5 FB4_12 67 I/O I (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 68 I/O I (unused) 0 0 0 5 FB4_15 69 I/O I (unused) 0 0 0 5 FB4_16 (b) MyCore/MyClock/phi0D8 1 0 0 4 FB4_17 70 I/O I MyCore/MyClock/phi0D7 1 0 0 4 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: MyCore/MyClock/phi0D6 2: MyCore/MyClock/phi0D7 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyCore/MyClock/phi0D8 .X...................................... 1 1 MyCore/MyClock/phi0D7 X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) nslowbusclr 3 0 0 2 FB5_2 32 I/O O rnw 3 0 0 2 FB5_3 33 I/O O (unused) 0 0 0 5 FB5_4 (b) loop1out 0 0 0 5 FB5_5 34 I/O O (unused) 0 0 0 5 FB5_6 35 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O (unused) 0 0 0 5 FB5_9 37 I/O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 39 I/O I (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 \/3 2 FB5_13 (b) (b) nramcs<0> 10 5<- 0 0 FB5_14 41 I/O O nramcs<1> 1 0 /\2 2 FB5_15 43 I/O O MyCore/isslow8/MyCore/isslow8_D2 1 0 0 4 FB5_16 (b) (b) MyCore/ctrlsel/MyCore/ctrlsel_D2 1 0 0 4 FB5_17 44 I/O I MyCore/isorig/MyCore/isorig_D2 4 0 0 1 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$115 12: cpuaddr_ismyio 23: cpuaddrin_64k<18> 2: $OpTx$FX_DC$119 13: cpuaddrin_16<1> 24: cpuaddrin_64k<19> 3: MyCore/bootrom 14: cpuaddrin_16<2> 25: cpuaddrin_64k<20> 4: MyCore/fastvread 15: cpuaddrin_16<3> 26: cpuaddrin_64k<21> 5: MyCore/isorig/MyCore/isorig_D2 16: cpuaddrin_2k<11> 27: cpuaddrin_64k<22> 6: MyCore/isslow8/MyCore/isslow8_D2 17: cpuaddrin_2k<12> 28: cpuaddrin_64k<23> 7: MyCore/slow64k 18: cpuaddrin_2k<13> 29: cpuclk 8: MyCore/slowaccess 19: cpuaddrin_2k<14> 30: cpurnw 9: MyCore/slowdetected 20: cpuaddrin_2k<15> 31: nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 10: MyCore/wprotect<0> 21: cpuaddrin_64k<16> 32: reset 11: MyCore/wprotect<1> 22: cpuaddrin_64k<17> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs nslowbusclr ....X..XX.....................XX........ 5 5 rnw ....X..XX....................XXX........ 6 6 loop1out ........................................ 0 0 nramcs<0> .XX.X....XX......XXXXXXXXXXXXX.......... 18 18 nramcs<1> .X.....................XXXXXX........... 7 7 MyCore/isslow8/MyCore/isslow8_D2 ...X............XXXXXXXXXXXX.X.......... 14 14 MyCore/ctrlsel/MyCore/ctrlsel_D2 ...........XXXXXXXXXXXXXXXXX............ 17 17 MyCore/isorig/MyCore/isorig_D2 X.X..XX........XXXXXXXXXXXXX............ 17 17 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 45 I/O (unused) 0 0 0 5 FB6_3 46 I/O MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2 1 0 0 4 FB6_4 (b) (b) MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2 1 0 0 4 FB6_5 47 I/O (b) MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2 1 0 0 4 FB6_6 48 I/O (b) MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2 1 0 0 4 FB6_7 (b) (b) nromwe 1 0 0 4 FB6_8 50 I/O O diag 4 0 0 1 FB6_9 51 I/O O MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 1 0 0 4 FB6_10 (b) (b) latchen 1 0 0 4 FB6_11 52 I/O O nromcs 3 0 0 2 FB6_12 53 I/O O MyCore/useslowclk 4 0 0 1 FB6_13 (b) (b) MyCore/fastvread 4 0 0 1 FB6_14 54 I/O I MyCore/clklatch<3> 4 0 0 1 FB6_15 55 I/O I MyCore/clklatch<2> 4 0 0 1 FB6_16 (b) (b) MyCore/clklatch<4> 5 0 0 0 FB6_17 56 I/O I MyCore/clklatch<0> 5 0 0 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$119 12: MyCore/prgrom 23: cpuaddrin_64k<23> 2: MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 13: MyCore/slowaccess 24: cpuclk 3: MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 14: MyCore/slowdetected 25: cpudata<0> 4: MyCore/bootrom 15: MyCore/useslowclk 26: cpudata<2> 5: MyCore/clklatch<0> 16: cpuaddrin_64k<16> 27: cpudata<3> 6: MyCore/clklatch<2> 17: cpuaddrin_64k<17> 28: cpudata<4> 7: MyCore/clklatch<3> 18: cpuaddrin_64k<18> 29: cpurnw 8: MyCore/clklatch<4> 19: cpuaddrin_64k<19> 30: diag 9: MyCore/ctrlsel/MyCore/ctrlsel_D2 20: cpuaddrin_64k<20> 31: phi1in 10: MyCore/fastvread 21: cpuaddrin_64k<21> 32: reset 11: MyCore/isorig/MyCore/isorig_D2 22: cpuaddrin_64k<22> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2 .......X......X......................... 2 2 MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2 ......X.......X......................... 2 2 MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2 .....X........X......................... 2 2 MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2 ....X.........X......................... 2 2 nromwe X.................XXXXXX....X........... 8 8 diag ........X....X..............XX.X........ 5 5 MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 ..X.....X...................X........... 3 3 latchen .......................X................ 1 1 nromcs X..X......XXX..XXXXXXXX.....X.X......... 15 15 MyCore/useslowclk .X...........XX............X...X........ 5 5 MyCore/fastvread .X.......X...X...........X.....X........ 5 5 MyCore/clklatch<3> ..X...X......X............X....X........ 5 5 MyCore/clklatch<2> ..X..X.......X...........X.....X........ 5 5 MyCore/clklatch<4> ..X....X.....X...........XXX...X........ 7 7 MyCore/clklatch<0> ..X.X........X..........XXX....X........ 7 7 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$114 <= ((NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2) OR (MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2) OR (MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2) OR (MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2) OR (MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2)); $OpTx$FX_DC$115 <= (MyCore/hidebogus AND NOT cpuvpa AND NOT cpuvda); $OpTx$FX_DC$119 <= ((NOT reset) OR (NOT cpuvpa AND NOT cpuvda)); FDCPE_MyCore/MyClock/phi0D1: FDCPE port map (MyCore/MyClock/phi0D1,NOT phi1in,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D2: FDCPE port map (MyCore/MyClock/phi0D2,MyCore/MyClock/phi0D1,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D2a: FDCPE port map (MyCore/MyClock/phi0D2a,MyCore/MyClock/phi0D2,fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D3: FDCPE port map (MyCore/MyClock/phi0D3,MyCore/MyClock/phi0D2,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D4: FDCPE port map (MyCore/MyClock/phi0D4,MyCore/MyClock/phi0D3,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D5: FDCPE port map (MyCore/MyClock/phi0D5,MyCore/MyClock/phi0D4,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D6: FDCPE port map (MyCore/MyClock/phi0D6,MyCore/MyClock/phi0D5,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D7: FDCPE port map (MyCore/MyClock/phi0D7,MyCore/MyClock/phi0D6,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D8: FDCPE port map (MyCore/MyClock/phi0D8,MyCore/MyClock/phi0D7,NOT fastclkin,'0','0'); FDCPE_MyCore/MyClock/phi0D9: FDCPE port map (MyCore/MyClock/phi0D9,MyCore/MyClock/phi0D8,MyCore/fastclkby2,'0','0'); FDCPE_MyCore/MyClock/phi0DA: FDCPE port map (MyCore/MyClock/phi0DA,MyCore/MyClock/phi0D9,MyCore/fastclkby2,'0','0'); FDCPE_MyCore/MyClock/phi0DB: FDCPE port map (MyCore/MyClock/phi0DB,MyCore/MyClock/phi0DA,MyCore/fastclkby2,'0','0'); FDCPE_MyCore/MyClock/phi0DC: FDCPE port map (MyCore/MyClock/phi0DC,MyCore/MyClock/phi0DB,MyCore/fastclkby2,'0','0'); FDCPE_MyCore/MyClock/phi0DD: FDCPE port map (MyCore/MyClock/phi0DD,MyCore/MyClock/phi0DC,MyCore/fastclkby2,'0','0'); FDCPE_MyCore/MyClockSync/slowdone: FDCPE port map (MyCore/MyClockSync/slowdone,MyCore/MyClockSync/slowdone_D,phi1in,MyCore/MyClockSync/slowdone_CLR,'0'); MyCore/MyClockSync/slowdone_D <= ((MyCore/slowaccess AND rdy) OR (MyCore/MyClockSync/slowdone AND NOT rdy)); MyCore/MyClockSync/slowdone_CLR <= (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND MyCore/MyClock/phi0D2a); MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 <= (NOT cpurnw AND MyCore/ctrlsel/MyCore/ctrlsel_D2 AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2); MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 <= (NOT cpurnw AND NOT cpuaddrin_16(0) AND MyCore/ctrlsel/MyCore/ctrlsel_D2); FTCPE_MyCore/Mytiming/bydiv: FTCPE port map (MyCore/Mytiming/bydiv,MyCore/Mytiming/bydiv_T,NOT fastclkin,NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF,'0'); MyCore/Mytiming/bydiv_T <= (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3)); MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF <= (reset AND MyCore/clkenable); FDCPE_MyCore/Mytiming/bydivx: FDCPE port map (MyCore/Mytiming/bydivx,MyCore/Mytiming/bydiv,fastclkin,NOT reset,'0'); FDCPE_MyCore/Mytiming/clkcounter0: FDCPE port map (MyCore/Mytiming/clkcounter(0),MyCore/Mytiming/clkcounter_D(0),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(0),MyCore/Mytiming/clkcounter_PRE(0)); MyCore/Mytiming/clkcounter_D(0) <= ((NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2) OR (NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2) OR (NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv AND MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2) OR (MyCore/Mytiming/clkcounter(0) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF)); MyCore/Mytiming/clkcounter_CLR(0) <= (NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF); MyCore/Mytiming/clkcounter_PRE(0) <= (MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF); FDCPE_MyCore/Mytiming/clkcounter1: FDCPE port map (MyCore/Mytiming/clkcounter(1),MyCore/Mytiming/clkcounter_D(1),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(1),MyCore/Mytiming/clkcounter_PRE(1)); MyCore/Mytiming/clkcounter_D(1) <= ((NOT MyCore/Mytiming/clkcounter(0) AND MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND NOT $OpTx$FX_DC$114) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND NOT $OpTx$FX_DC$114)); MyCore/Mytiming/clkcounter_CLR(1) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2); MyCore/Mytiming/clkcounter_PRE(1) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2); FDCPE_MyCore/Mytiming/clkcounter2: FDCPE port map (MyCore/Mytiming/clkcounter(2),MyCore/Mytiming/clkcounter_D(2),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(2),MyCore/Mytiming/clkcounter_PRE(2)); MyCore/Mytiming/clkcounter_D(2) <= ((MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND $OpTx$FX_DC$114 AND MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2) OR (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2) OR (NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND NOT $OpTx$FX_DC$114 AND NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2)); MyCore/Mytiming/clkcounter_CLR(2) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2); MyCore/Mytiming/clkcounter_PRE(2) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2); FTCPE_MyCore/Mytiming/clkcounter3: FTCPE port map (MyCore/Mytiming/clkcounter(3),MyCore/Mytiming/clkcounter_T(3),NOT fastclkin,MyCore/Mytiming/clkcounter_CLR(3),MyCore/Mytiming/clkcounter_PRE(3)); MyCore/Mytiming/clkcounter_T(3) <= ((MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/clkcounter(3) AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(3) AND NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND NOT MyCore/Mytiming/clkcounter(3) AND MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2) OR (NOT MyCore/Mytiming/clkcounter(0) AND NOT MyCore/Mytiming/clkcounter(1) AND NOT MyCore/Mytiming/clkcounter(2) AND MyCore/Mytiming/bydiv AND NOT MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 AND MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 AND MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 AND NOT MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 AND NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2)); MyCore/Mytiming/clkcounter_CLR(3) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND NOT MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2); MyCore/Mytiming/clkcounter_PRE(3) <= (NOT MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF AND MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2); FDCPE_MyCore/bootrom: FDCPE port map (MyCore/bootrom,MyCore/bootrom_D,NOT MyCore/slowdetected,MyCore/bootrom_CLR,MyCore/bootrom_PRE); MyCore/bootrom_D <= ((MyCore/bootrom AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(6) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); MyCore/bootrom_CLR <= (NOT reset AND NOT bootromin); MyCore/bootrom_PRE <= (NOT reset AND bootromin); FDCPE_MyCore/clkenable: FDCPE port map (MyCore/clkenable,'1',MyCore/clkenable_C,MyCore/clkenable_CLR,NOT reset); MyCore/clkenable_C <= (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND MyCore/MyClock/phi0D2a); MyCore/clkenable_CLR <= (reset AND MyCore/slowdetected); FDCPE_MyCore/clklatch0: FDCPE port map (MyCore/clklatch(0),MyCore/clklatch_D(0),NOT MyCore/slowdetected,'0',NOT reset); MyCore/clklatch_D(0) <= ((NOT MyCore/clklatch(0) AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND cpudata(3) AND NOT cpudata(0) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND cpudata(2) AND NOT cpudata(0) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); FDCPE_MyCore/clklatch1: FDCPE port map (MyCore/clklatch(1),MyCore/clklatch_D(1),NOT MyCore/slowdetected,'0',NOT reset); MyCore/clklatch_D(1) <= ((reset AND cpudata(3) AND NOT cpudata(1) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (NOT MyCore/clklatch(1) AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND cpudata(2) AND NOT cpudata(1) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); FDCPE_MyCore/clklatch2: FDCPE port map (MyCore/clklatch(2),MyCore/clklatch_D(2),NOT MyCore/slowdetected,'0',NOT reset); MyCore/clklatch_D(2) <= ((NOT MyCore/clklatch(2) AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND NOT cpudata(2) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); FDCPE_MyCore/clklatch3: FDCPE port map (MyCore/clklatch(3),MyCore/clklatch_D(3),NOT MyCore/slowdetected,'0',NOT reset); MyCore/clklatch_D(3) <= ((NOT MyCore/clklatch(3) AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND NOT cpudata(3) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); FDCPE_MyCore/clklatch4: FDCPE port map (MyCore/clklatch(4),MyCore/clklatch_D(4),NOT MyCore/slowdetected,NOT reset,'0'); MyCore/clklatch_D(4) <= ((MyCore/clklatch(4) AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND cpudata(3) AND cpudata(4) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (reset AND cpudata(2) AND cpudata(4) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(0)); MyCore/clklatchx(1)/MyCore/clklatchx(1)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(1)); MyCore/clklatchx(2)/MyCore/clklatchx(2)_D2 <= (NOT MyCore/useslowclk AND NOT MyCore/clklatch(2)); MyCore/clklatchx(3)/MyCore/clklatchx(3)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(3)); MyCore/clklatchx(4)/MyCore/clklatchx(4)_D2 <= (NOT MyCore/useslowclk AND MyCore/clklatch(4)); MyCore/ctrlsel/MyCore/ctrlsel_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_2k(15) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_2k(12)); FTCPE_MyCore/fastclkby2: FTCPE port map (MyCore/fastclkby2,'1',NOT fastclkin,NOT reset,'0'); FDCPE_MyCore/fastmode: FDCPE port map (MyCore/fastmode,MyCore/fastmode_D,NOT MyCore/slowdetected,'0',NOT reset); MyCore/fastmode_D <= ((MyCore/fastmode AND NOT MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2) OR (cpudata(7) AND MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2)); FDCPE_MyCore/fastvread: FDCPE port map (MyCore/fastvread,MyCore/fastvread_D,NOT MyCore/slowdetected,NOT reset,'0'); MyCore/fastvread_D <= ((MyCore/fastvread AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(2) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); FDCPE_MyCore/hidebogus: FDCPE port map (MyCore/hidebogus,MyCore/hidebogus_D,NOT MyCore/slowdetected,NOT reset,'0'); MyCore/hidebogus_D <= ((MyCore/hidebogus AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(3) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); MyCore/isorig/MyCore/isorig_D2 <= ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT $OpTx$FX_DC$115) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT MyCore/bootrom AND MyCore/slow64k AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(12) AND NOT $OpTx$FX_DC$115) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(12) AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115)); MyCore/isslow8/MyCore/isslow8_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpurnw AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND MyCore/fastvread AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(12)); FDCPE_MyCore/prgrom: FDCPE port map (MyCore/prgrom,MyCore/prgrom_D,NOT MyCore/slowdetected,NOT reset,'0'); MyCore/prgrom_D <= ((MyCore/prgrom AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(7) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); FDCPE_MyCore/slow64k: FDCPE port map (MyCore/slow64k,MyCore/slow64k_D,NOT MyCore/slowdetected,'0',NOT reset); MyCore/slow64k_D <= ((MyCore/slow64k AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(5) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); FDCPE_MyCore/slowaccess: FDCPE port map (MyCore/slowaccess,MyCore/slowdetected,MyCore/slowaccess/MyCore/slowaccess_CLKF,MyCore/slowaccess/MyCore/slowaccess_RSTF,'0'); MyCore/slowaccess/MyCore/slowaccess_CLKF <= ((MyCore/fastmode AND phi1in AND NOT MyCore/MyClock/phi0D7) OR (NOT MyCore/fastmode AND phi1in AND NOT MyCore/MyClock/phi0DC)); MyCore/slowaccess/MyCore/slowaccess_RSTF <= ((NOT reset) OR (NOT MyCore/slowdetected AND NOT MyCore/MyClock/phi0D2 AND MyCore/MyClock/phi0D2a)); FDCPE_MyCore/slowdetected: FDCPE port map (MyCore/slowdetected,MyCore/slowdetected_D,cpuclk,NOT MyCore/slowdetected/MyCore/slowdetected_RSTF,'0'); MyCore/slowdetected_D <= ((MyCore/useslowclk) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND MyCore/bootrom) OR (MyCore/isorig/MyCore/isorig_D2 AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT MyCore/isslow8/MyCore/isslow8_D2 AND NOT $OpTx$FX_DC$115)); MyCore/slowdetected/MyCore/slowdetected_RSTF <= (reset AND NOT MyCore/MyClockSync/slowdone); FDCPE_MyCore/useslowclk: FDCPE port map (MyCore/useslowclk,MyCore/useslowclk_D,NOT MyCore/slowdetected,'0',NOT reset); MyCore/useslowclk_D <= ((MyCore/useslowclk AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(4) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); FDCPE_MyCore/wprotect0: FDCPE port map (MyCore/wprotect(0),MyCore/wprotect_D(0),NOT MyCore/slowdetected,NOT reset,'0'); MyCore/wprotect_D(0) <= ((MyCore/wprotect(0) AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(0) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); FDCPE_MyCore/wprotect1: FDCPE port map (MyCore/wprotect(1),MyCore/wprotect_D(1),NOT MyCore/slowdetected,NOT reset,'0'); MyCore/wprotect_D(1) <= ((MyCore/wprotect(1) AND NOT MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2) OR (cpudata(1) AND MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2)); cpuclk <= NOT (((NOT MyCore/slowdetected AND NOT MyCore/Mytiming/bydiv AND NOT MyCore/slowaccess) OR (NOT MyCore/slowdetected AND NOT MyCore/slowaccess AND NOT MyCore/Mytiming/bydivx AND NOT MyCore/clklatchx(0)/MyCore/clklatchx(0)_D2))); cpuwnr <= NOT cpurnw; FDCPE_diag: FDCPE port map (diag,diag_D,NOT MyCore/slowdetected,NOT reset,'0'); diag_D <= ((cpurnw AND MyCore/ctrlsel/MyCore/ctrlsel_D2) OR (diag AND NOT MyCore/ctrlsel/MyCore/ctrlsel_D2)); latchen <= NOT cpuclk; loop1out <= '0'; loop2out <= '0'; nramcs(0) <= NOT (((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT MyCore/bootrom AND cpurnw AND cpuclk AND NOT MyCore/isorig/MyCore/isorig_D2 AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND cpuclk AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND cpuclk AND MyCore/wprotect(1) AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND cpuclk AND NOT MyCore/wprotect(0) AND NOT MyCore/wprotect(1) AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(13) AND cpuclk AND MyCore/wprotect(0) AND MyCore/wprotect(1) AND NOT $OpTx$FX_DC$119) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuclk AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(18) AND cpuclk AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(17) AND cpuclk AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(16) AND cpuclk AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND cpuclk AND NOT cpuaddrin_2k(15) AND NOT $OpTx$FX_DC$119))); nramcs(1) <= NOT ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuclk AND NOT $OpTx$FX_DC$119)); nromcs <= NOT (((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpurnw AND MyCore/slowaccess AND NOT phi1in AND NOT $OpTx$FX_DC$119) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND MyCore/slowaccess AND NOT phi1in AND MyCore/prgrom AND NOT $OpTx$FX_DC$119) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND MyCore/bootrom AND cpurnw AND MyCore/slowaccess AND NOT phi1in AND NOT MyCore/isorig/MyCore/isorig_D2 AND NOT $OpTx$FX_DC$119))); nromwe <= NOT ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpurnw AND cpuclk AND NOT $OpTx$FX_DC$119)); FDCPE_nslowbusclr: FDCPE port map (nslowbusclr,'0',nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,NOT reset,nslowbusclr_PRE); nslowbusclr_PRE <= (MyCore/slowdetected AND MyCore/slowaccess AND MyCore/isorig/MyCore/isorig_D2); FDCPE_nslowdataenout: FDCPE port map (nslowdataenout,nslowdataenout_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,'0',MyCore/slowaccess/MyCore/slowaccess_RSTF); nslowdataenout_D <= (MyCore/slowdetected AND MyCore/slowaccess AND NOT MyCore/ctrlsel/MyCore/ctrlsel_D2 AND MyCore/isorig/MyCore/isorig_D2); nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF <= ((MyCore/fastmode AND NOT MyCore/MyClock/phi0D2 AND NOT MyCore/MyClock/phi0D8) OR (NOT MyCore/fastmode AND NOT MyCore/MyClock/phi0D2 AND NOT MyCore/MyClock/phi0DD)); phi1 <= NOT phi0; phi2 <= NOT phi1in; FDCPE_rnw: FDCPE port map (rnw,rnw_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,'0',NOT reset); rnw_D <= (NOT cpurnw AND MyCore/slowdetected AND MyCore/slowaccess AND MyCore/isorig/MyCore/isorig_D2); FDCPE_slowaddrlatch: FDCPE port map (slowaddrlatch,slowaddrlatch_D,nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF,slowaddrlatch_CLR,NOT reset); slowaddrlatch_D <= (MyCore/slowdetected AND MyCore/slowaccess AND MyCore/isorig/MyCore/isorig_D2); slowaddrlatch_CLR <= (reset AND MyCore/slowaccess/MyCore/slowaccess_RSTF); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-15-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-15-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 cpuaddrin_2k<12> 43 nramcs<1> 2 cpuaddrin_2k<13> 44 phi1in 3 cpuaddrin_2k<14> 45 TIE 4 cpuaddrin_2k<15> 46 TIE 5 cpuaddrin_2k<11> 47 TIE 6 cpuclk 48 TIE 7 nslowdataenout 49 GND 8 GND 50 nromwe 9 phi0 51 diag 10 fastclkin 52 latchen 11 cpuvpa 53 nromcs 12 phi2 54 cpudata<1> 13 cpuvda 55 cpudata<0> 14 TIE 56 cpudata<3> 15 TIE 57 cpudata<2> 16 GND 58 cpudata<4> 17 cpurnw 59 TDO 18 reset 60 GND 19 bootromin 61 cpudata<6> 20 slowaddrlatch 62 cpudata<7> 21 TIE 63 cpudata<5> 22 VCC 64 VCC 23 phi1 65 TIE 24 TIE 66 cpuaddrin_64k<23> 25 cpuaddr_ismyio 67 cpuaddrin_64k<22> 26 TIE 68 cpuaddrin_64k<21> 27 GND 69 cpuaddrin_64k<20> 28 TDI 70 cpuaddrin_64k<19> 29 TMS 71 cpuaddrin_64k<16> 30 TCK 72 cpuaddrin_64k<17> 31 loop2out 73 VCC 32 nslowbusclr 74 TIE 33 rnw 75 cpuaddrin_64k<18> 34 loop1out 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 TIE 79 cpuwnr 38 VCC 80 TIE 39 rdy 81 cpuaddrin_16<1> 40 TIE 82 cpuaddrin_16<0> 41 nramcs<0> 83 cpuaddrin_16<3> 42 GND 84 cpuaddrin_16<2> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-15-PC84 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : OFF Pin Feedback : OFF Input Limit : 36 Pterm Limit : 90