Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
MyCore/Mytiming/clkcounter<3> 11 11 FB1 MC1 STD     (b) (b) SET
MyCore/slowaccess/MyCore/slowaccess_RSTF 2 4 FB1 MC4 STD     (b) (b)  
MyCore/Mytiming/bydivx 2 2 FB1 MC5 STD   3 I/O I RESET
MyCore/Mytiming/bydiv 2 5 FB1 MC6 STD   4 I/O I RESET
MyCore/slowaccess 3 3 FB1 MC7 STD     (b) (b) RESET
MyCore/clkenable 3 4 FB1 MC8 STD   5 I/O I RESET
cpuclk 2 5 FB1 MC9 STD FAST 6 I/O O  
MyCore/MyClockSync/slowdone 4 7 FB1 MC10 STD     (b) (b) RESET
nslowdataenout 3 6 FB1 MC11 STD FAST 7 I/O O RESET
MyCore/clklatch<1> 5 7 FB1 MC12 STD   9 I/O/GCK1 I RESET
$OpTx$FX_DC$114 5 8 FB1 MC13 STD     (b) (b)  
MyCore/Mytiming/clkcounter<1> 7 10 FB1 MC14 STD   10 I/O/GCK2 GCK SET
MyCore/Mytiming/clkcounter<0> 7 8 FB1 MC15 STD   11 I/O I SET
phi2 1 1 FB1 MC16 STD FAST 12 I/O/GCK3 O  
MyCore/slowdetected/MyCore/slowdetected_RSTF 1 2 FB1 MC17 STD   13 I/O I  
MyCore/Mytiming/clkcounter<2> 8 7 FB1 MC18 STD     (b) (b) SET
MyCore/fastclkby2 1 1 FB2 MC3 STD   72 I/O I RESET
MyCore/clklatchx<1>/MyCore/clklatchx<1>_D2 1 2 FB2 MC4 STD     (b) (b)  
MyCore/Mytiming/bydiv/MyCore/Mytiming/bydiv_RSTF 1 2 FB2 MC5 STD   74 I/O/GSR (b)  
MyCore/MyControl/clklatch_or0000/MyCore/MyControl/clklatch_or0000_D2 1 3 FB2 MC6 STD   75 I/O I  
MyCore/MyClock/phi0D6 1 1 FB2 MC7 STD     (b) (b) RESET
MyCore/MyClock/phi0D5 1 1 FB2 MC8 STD   76 I/O/GTS1 (b) RESET
MyCore/MyClock/phi0D4 1 1 FB2 MC9 STD   77 I/O/GTS2 (b) RESET
MyCore/MyClock/phi0D3 1 1 FB2 MC10 STD     (b) (b) RESET
cpuwnr 1 1 FB2 MC11 STD FAST 79 I/O O  
MyCore/MyClock/phi0D2a 1 1 FB2 MC12 STD   80 I/O (b) RESET
MyCore/MyClock/phi0D2 1 1 FB2 MC13 STD     (b) (b) RESET
MyCore/MyClock/phi0D1 1 1 FB2 MC14 STD   81 I/O I RESET
MyCore/MyClock/phi0DC 2 2 FB2 MC15 STD   82 I/O I RESET
MyCore/MyClock/phi0DB 2 2 FB2 MC16 STD   83 I/O I RESET
MyCore/MyClock/phi0DA 2 2 FB2 MC17 STD   84 I/O I RESET
MyCore/slowdetected 6 15 FB2 MC18 STD     (b) (b) RESET
$OpTx$FX_DC$115 1 3 FB3 MC3 STD   15 I/O (b)  
nslowdataenout_OBUF/nslowdataenout_OBUF_CLKF 2 4 FB3 MC4 STD     (b) (b)  
MyCore/slowaccess/MyCore/slowaccess_CLKF 2 4 FB3 MC5 STD   17 I/O I  
MyCore/MyClock/phi0DD 2 2 FB3 MC6 STD   18 I/O I RESET
MyCore/MyClock/phi0D9 2 2 FB3 MC7 STD     (b) (b) RESET
$OpTx$FX_DC$119 2 3 FB3 MC8 STD   19 I/O I  
slowaddrlatch 4 6 FB3 MC9 STD FAST 20 I/O O RESET
MyCore/wprotect<1> 4 5 FB3 MC10 STD     (b) (b) RESET
MyCore/wprotect<0> 4 5 FB3 MC11 STD   21 I/O (b) RESET
phi1 1 1 FB3 MC12 STD FAST 23 I/O O  
MyCore/slow64k 4 5 FB3 MC13 STD     (b) (b) RESET
MyCore/prgrom 4 5 FB3 MC14 STD   24 I/O (b) RESET
MyCore/hidebogus 4 5 FB3 MC15 STD   25 I/O I RESET
MyCore/fastmode 4 5 FB3 MC16 STD   26 I/O (b) RESET
loop2out 0 0 FB3 MC17 STD FAST 31 I/O O  
MyCore/bootrom 5 6 FB3 MC18 STD     (b) (b) RESET
MyCore/MyClock/phi0D8 1 1 FB4 MC17 STD   70 I/O I RESET
MyCore/MyClock/phi0D7 1 1 FB4 MC18 STD     (b) (b) RESET
nslowbusclr 3 5 FB5 MC2 STD FAST 32 I/O O RESET
rnw 3 6 FB5 MC3 STD FAST 33 I/O O RESET
loop1out 0 0 FB5 MC5 STD FAST 34 I/O O  
nramcs<0> 10 18 FB5 MC14 STD FAST 41 I/O O  
nramcs<1> 1 7 FB5 MC15 STD FAST 43 I/O O  
MyCore/isslow8/MyCore/isslow8_D2 1 14 FB5 MC16 STD     (b) (b)  
MyCore/ctrlsel/MyCore/ctrlsel_D2 1 17 FB5 MC17 STD   44 I/O I  
MyCore/isorig/MyCore/isorig_D2 4 17 FB5 MC18 STD     (b) (b)  
MyCore/clklatchx<4>/MyCore/clklatchx<4>_D2 1 2 FB6 MC4 STD     (b) (b)  
MyCore/clklatchx<3>/MyCore/clklatchx<3>_D2 1 2 FB6 MC5 STD   47 I/O (b)  
MyCore/clklatchx<2>/MyCore/clklatchx<2>_D2 1 2 FB6 MC6 STD   48 I/O (b)  
MyCore/clklatchx<0>/MyCore/clklatchx<0>_D2 1 2 FB6 MC7 STD     (b) (b)  
nromwe 1 8 FB6 MC8 STD FAST 50 I/O O  
diag 4 5 FB6 MC9 STD FAST 51 I/O O RESET
MyCore/MyControl/bootrom_or0000/MyCore/MyControl/bootrom_or0000_D2 1 3 FB6 MC10 STD     (b) (b)  
latchen 1 1 FB6 MC11 STD FAST 52 I/O O  
nromcs 3 15 FB6 MC12 STD FAST 53 I/O O  
MyCore/useslowclk 4 5 FB6 MC13 STD     (b) (b) RESET
MyCore/fastvread 4 5 FB6 MC14 STD   54 I/O I RESET
MyCore/clklatch<3> 4 5 FB6 MC15 STD   55 I/O I RESET
MyCore/clklatch<2> 4 5 FB6 MC16 STD     (b) (b) RESET
MyCore/clklatch<4> 5 7 FB6 MC17 STD   56 I/O I RESET
MyCore/clklatch<0> 5 7 FB6 MC18 STD     (b) (b) RESET