Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|
BUF_masterclk | 2 | 5 | FB1 | MC13 | STD | (b) | (b) | |||
MyClockSync/slowdone | 3 | 6 | FB6 | MC15 | STD | 55 | I/O | I | RESET | |
MyClock/phi0D1 | 1 | 1 | FB1 | MC7 | STD | (b) | (b) | RESET | ||
MyClock/phi0D2 | 1 | 1 | FB1 | MC6 | STD | 4 | I/O | I | RESET | |
MyClock/phi0D3 | 1 | 1 | FB1 | MC5 | STD | 3 | I/O | I | RESET | |
MyClock/phi0D4 | 1 | 1 | FB2 | MC12 | STD | 80 | I/O | (b) | RESET | |
MyClock/phi0D5 | 1 | 1 | FB2 | MC10 | STD | (b) | (b) | RESET | ||
MyClock/phi0D6 | 1 | 1 | FB2 | MC9 | STD | 77 | I/O/GTS2 | (b) | RESET | |
MyClock/phi0D7 | 1 | 1 | FB2 | MC8 | STD | 76 | I/O/GTS1 | (b) | RESET | |
MyClock/phi0D8 | 1 | 1 | FB2 | MC7 | STD | (b) | (b) | RESET | ||
MyClock/phi0D9 | 2 | 2 | FB2 | MC18 | STD | (b) | (b) | RESET | ||
MyClock/phi0DA | 2 | 2 | FB2 | MC17 | STD | 84 | I/O | I | RESET | |
MyClock/phi0DB | 2 | 2 | FB2 | MC16 | STD | 83 | I/O | I | RESET | |
MyClock/phi0DC | 2 | 2 | FB2 | MC15 | STD | 82 | I/O | I | RESET | |
MyClock/phi0DD | 2 | 2 | FB2 | MC14 | STD | 81 | I/O | I | RESET | |
MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 | 1 | 19 | FB5 | MC13 | STD | (b) | (b) | |||
MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 | 1 | 19 | FB5 | MC12 | STD | 40 | I/O | (b) | ||
Mytiming/clkcounter<0> | 7 | 8 | FB1 | MC1 | STD | (b) | (b) | SET | ||
Mytiming/clkcounter<1> | 7 | 10 | FB1 | MC15 | STD | 11 | I/O | I | SET | |
Mytiming/clkcounter<2> | 8 | 7 | FB1 | MC2 | STD | 1 | I/O | I | SET | |
Mytiming/clkcounter<3> | 7 | 7 | FB1 | MC14 | STD | 10 | I/O/GCK2 | GCK | SET | |
$OpTx$FX_DC$91 | 2 | 4 | FB6 | MC14 | STD | 54 | I/O | I | ||
$OpTx$FX_DC$97 | 1 | 4 | FB1 | MC10 | STD | (b) | (b) | |||
$OpTx$FX_DC$98 | 1 | 5 | FB1 | MC8 | STD | 5 | I/O | I | ||
bootrom | 5 | 6 | FB3 | MC18 | STD | (b) | (b) | RESET | ||
clkenable | 3 | 4 | FB5 | MC17 | STD | 44 | I/O | (b) | RESET | |
clklatch<0> | 5 | 7 | FB3 | MC17 | STD | 31 | I/O | (b) | RESET | |
clklatch<1> | 5 | 7 | FB3 | MC16 | STD | 26 | I/O | (b) | RESET | |
clklatch<2> | 4 | 5 | FB3 | MC14 | STD | 24 | I/O | (b) | RESET | |
clklatch<3> | 4 | 5 | FB3 | MC13 | STD | (b) | (b) | RESET | ||
clklatch<4> | 5 | 7 | FB3 | MC15 | STD | 25 | I/O | I | RESET | |
clklatchx<0>/clklatchx<0>_D2 | 1 | 2 | FB2 | MC6 | STD | 75 | I/O | I | ||
clklatchx<1>/clklatchx<1>_D2 | 1 | 2 | FB2 | MC5 | STD | 74 | I/O/GSR | (b) | ||
clklatchx<2>/clklatchx<2>_D2 | 1 | 2 | FB2 | MC4 | STD | (b) | (b) | |||
clklatchx<3>/clklatchx<3>_D2 | 1 | 2 | FB2 | MC3 | STD | 72 | I/O | I | ||
clklatchx<4>/clklatchx<4>_D2 | 1 | 2 | FB4 | MC18 | STD | (b) | (b) | |||
cpuclk | 1 | 1 | FB1 | MC9 | STD | FAST | 6 | I/O | O | |
cpuwnr | 1 | 1 | FB2 | MC11 | STD | FAST | 79 | I/O | O | |
fastclkby2 | 1 | 1 | FB1 | MC18 | STD | (b) | (b) | RESET | ||
fastmode | 4 | 5 | FB3 | MC11 | STD | 21 | I/O | (b) | RESET | |
fastvread | 4 | 5 | FB3 | MC10 | STD | (b) | (b) | RESET | ||
hidebogus | 4 | 5 | FB6 | MC17 | STD | 56 | I/O | I | RESET | |
isorig/isorig_D2 | 8 | 21 | FB5 | MC18 | STD | (b) | (b) | |||
latchen | 1 | 3 | FB6 | MC11 | STD | FAST | 52 | I/O | O | |
masterclk | 2 | 2 | FB1 | MC12 | STD | 9 | I/O/GCK1 | GCK/I | RESET | |
masterclk/masterclk_RSTF | 1 | 2 | FB1 | MC17 | STD | 13 | I/O | I | ||
nramcs<0> | 10 | 17 | FB5 | MC14 | STD | FAST | 41 | I/O | O | |
nramcs<1> | 1 | 6 | FB5 | MC15 | STD | FAST | 43 | I/O | O | |
nromcs | 3 | 15 | FB6 | MC12 | STD | FAST | 53 | I/O | O | |
nromwe | 1 | 7 | FB6 | MC8 | STD | FAST | 50 | I/O | O | |
nslowbusclr | 3 | 4 | FB5 | MC2 | STD | FAST | 32 | I/O | O | RESET |
nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF | 2 | 3 | FB2 | MC13 | STD | (b) | (b) | |||
nslowdataen | 4 | 7 | FB6 | MC16 | STD | (b) | (b) | RESET | ||
nslowdataenout | 2 | 2 | FB1 | MC11 | STD | FAST | 7 | I/O | O | RESET |
phi1 | 1 | 1 | FB3 | MC12 | STD | FAST | 23 | I/O | O | |
phi2 | 1 | 1 | FB1 | MC16 | STD | FAST | 12 | I/O/GCK3 | O | |
prgrom | 4 | 5 | FB3 | MC8 | STD | 19 | I/O | I | RESET | |
rnw | 3 | 5 | FB5 | MC3 | STD | FAST | 33 | I/O | O | RESET |
slow64k | 4 | 5 | FB3 | MC7 | STD | (b) | (b) | RESET | ||
slowaccess | 3 | 3 | FB3 | MC3 | STD | 15 | I/O | (b) | RESET | |
slowaccess/slowaccess_RSTF | 2 | 4 | FB5 | MC16 | STD | (b) | (b) | |||
slowaddrlatch | 4 | 5 | FB3 | MC9 | STD | FAST | 20 | I/O | O | RESET |
slowdetected | 7 | 11 | FB6 | MC18 | STD | (b) | (b) | RESET | ||
slowdetected/slowdetected_RSTF | 1 | 2 | FB6 | MC13 | STD | (b) | (b) | |||
useslowclk | 4 | 5 | FB3 | MC6 | STD | 18 | I/O | I | RESET | |
wprotect<0> | 4 | 5 | FB3 | MC5 | STD | 17 | I/O | I | RESET | |
wprotect<1> | 4 | 5 | FB3 | MC4 | STD | (b) | (b) | RESET |