Design Name | PET816 |
Device, Speed (SpeedFile Version) | XC95108, -15 (3.0) |
Date Created | Wed Aug 11 23:28:09 2010 |
Created By | Timing Report Generator: version L.33 |
Copyright | Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Possible asynchronous logic: Clock pin 'clkenable.CLKF' has multiple original clock nets 'MyClock/phi0D3.Q' 'MyClock/phi0D2.Q' 'slowdetected.Q'. |
Possible asynchronous logic: Clock pin 'slowaddrlatch.CLKF' has multiple original clock nets 'MyClock/phi0DD.Q' 'MyClock/phi0D7.Q' 'fastmode.Q'. |
Possible asynchronous logic: Clock pin 'rnw.CLKF' has multiple original clock nets 'MyClock/phi0DD.Q' 'MyClock/phi0D7.Q' 'fastmode.Q'. |
Possible asynchronous logic: Clock pin 'slowaccess.CLKF' has multiple original clock nets 'MyClock/phi0DD.Q' 'MyClock/phi0D7.Q' 'fastmode.Q'. |
Possible asynchronous logic: Clock pin 'nslowdataen.CLKF' has multiple original clock nets 'MyClock/phi0DD.Q' 'MyClock/phi0D7.Q' 'fastmode.Q'. |
Possible asynchronous logic: Clock pin 'nslowbusclr.CLKF' has multiple original clock nets 'MyClock/phi0DD.Q' 'MyClock/phi0D7.Q' 'fastmode.Q'. |
Possible asynchronous logic: Clock pin 'bootrom.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'useslowclk.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'slowdetected.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'wprotect<0>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'wprotect<1>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'fastmode.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<0>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<1>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<2>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<3>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<4>.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'fastvread.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'hidebogus.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'prgrom.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Possible asynchronous logic: Clock pin 'slow64k.CLKF' has multiple original clock nets 'slowaccess.Q' 'slowdetected.Q' 'masterclk.Q'. |
Performance Summary | |
---|---|
Min. Clock Period | 52.000 ns. |
Max. Clock Frequency (fSYSTEM) | 19.231 MHz. |
Limited by Cycle Time for fastclkin | |
Clock to Setup (tCYC) | 52.000 ns. |
Pad to Pad Delay (tPD) | 34.000 ns. |
Setup to Clock at the Pad (tSU) | 26.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 167.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
TS1003 | 0.0 | 0.0 | 0 | 0 |
TS1004 | 0.0 | 0.0 | 0 | 0 |
TS1005 | 0.0 | 0.0 | 0 | 0 |
TS1006 | 0.0 | 0.0 | 0 | 0 |
TS1007 | 0.0 | 0.0 | 0 | 0 |
TS1008 | 0.0 | 0.0 | 0 | 0 |
TS1009 | 0.0 | 0.0 | 0 | 0 |
TS1010 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 52.0 | 95 | 95 |
AUTO_TS_P2P | 0.0 | 167.0 | 73 | 73 |
AUTO_TS_P2F | 0.0 | 45.0 | 370 | 370 |
AUTO_TS_F2P | 0.0 | 57.0 | 31 | 31 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
Mytiming/clkcounter<0>.Q to Mytiming/clkcounter<1>.D | 0.000 | 52.000 | -52.000 |
Mytiming/clkcounter<0>.Q to Mytiming/clkcounter<2>.D | 0.000 | 52.000 | -52.000 |
Mytiming/clkcounter<0>.Q to Mytiming/clkcounter<3>.D | 0.000 | 52.000 | -52.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
fastclkin to nramcs<0> | 0.000 | 167.000 | -167.000 |
fastclkin to nromcs | 0.000 | 166.000 | -166.000 |
fastclkin to nramcs<1> | 0.000 | 152.000 | -152.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
cpuaddr_ismyio to bootrom.D | 0.000 | 45.000 | -45.000 |
cpuaddr_ismyio to fastvread.D | 0.000 | 45.000 | -45.000 |
cpuaddr_ismyio to hidebogus.D | 0.000 | 45.000 | -45.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
masterclk.Q to nramcs<0> | 0.000 | 57.000 | -57.000 |
slowaccess.Q to nramcs<0> | 0.000 | 57.000 | -57.000 |
slowdetected.Q to nramcs<0> | 0.000 | 57.000 | -57.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
fastclkby2.Q | 55.556 | Limited by Cycle Time for fastclkby2.Q |
MyClock/phi0D3.Q | 71.429 | Limited by Clock Pulse Width for MyClock/phi0D3.Q |
MyClock/phi0D2.Q | 71.429 | Limited by Clock Pulse Width for MyClock/phi0D2.Q |
phi0 | 55.556 | Limited by Cycle Time for phi0 |
MyClock/phi0DD.Q | 55.556 | Limited by Cycle Time for MyClock/phi0DD.Q |
MyClock/phi0D7.Q | 55.556 | Limited by Cycle Time for MyClock/phi0D7.Q |
fastmode.Q | 55.556 | Limited by Cycle Time for fastmode.Q |
fastclkin | 19.231 | Limited by Cycle Time for fastclkin |
slowaccess.Q | 27.778 | Limited by Cycle Time for slowaccess.Q |
slowdetected.Q | 27.778 | Limited by Cycle Time for slowdetected.Q |
masterclk.Q | 27.778 | Limited by Cycle Time for masterclk.Q |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
rdy | 8.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | -2.000 | 6.500 |
cpuaddrin_16<1> | -3.000 | 7.500 |
cpuaddrin_16<2> | -2.000 | 6.500 |
cpuaddrin_16<3> | -2.000 | 6.500 |
cpuaddrin_2k<11> | -2.000 | 6.500 |
cpuaddrin_2k<12> | -2.000 | 6.500 |
cpuaddrin_2k<13> | -2.000 | 6.500 |
cpuaddrin_2k<14> | -2.000 | 6.500 |
cpuaddrin_2k<15> | -2.000 | 6.500 |
cpuaddrin_64k<16> | -2.000 | 6.500 |
cpuaddrin_64k<17> | -2.000 | 6.500 |
cpuaddrin_64k<18> | -2.000 | 6.500 |
cpuaddrin_64k<19> | -2.000 | 6.500 |
cpuaddrin_64k<20> | -2.000 | 6.500 |
cpuaddrin_64k<21> | -2.000 | 6.500 |
cpuaddrin_64k<22> | -2.000 | 6.500 |
cpuaddrin_64k<23> | -2.000 | 6.500 |
cpurnw | -3.000 | 7.500 |
reset | -20.000 | 24.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | -2.000 | 6.500 |
cpuaddrin_16<1> | -3.000 | 7.500 |
cpuaddrin_16<2> | -2.000 | 6.500 |
cpuaddrin_16<3> | -2.000 | 6.500 |
cpuaddrin_2k<11> | -2.000 | 6.500 |
cpuaddrin_2k<12> | -2.000 | 6.500 |
cpuaddrin_2k<13> | -2.000 | 6.500 |
cpuaddrin_2k<14> | -2.000 | 6.500 |
cpuaddrin_2k<15> | -2.000 | 6.500 |
cpuaddrin_64k<16> | -2.000 | 6.500 |
cpuaddrin_64k<17> | -2.000 | 6.500 |
cpuaddrin_64k<18> | -2.000 | 6.500 |
cpuaddrin_64k<19> | -2.000 | 6.500 |
cpuaddrin_64k<20> | -2.000 | 6.500 |
cpuaddrin_64k<21> | -2.000 | 6.500 |
cpuaddrin_64k<22> | -2.000 | 6.500 |
cpuaddrin_64k<23> | -2.000 | 6.500 |
cpurnw | -3.000 | 7.500 |
reset | -20.000 | 24.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | -2.000 | 6.500 |
cpuaddrin_16<1> | -3.000 | 7.500 |
cpuaddrin_16<2> | -2.000 | 6.500 |
cpuaddrin_16<3> | -2.000 | 6.500 |
cpuaddrin_2k<11> | -2.000 | 6.500 |
cpuaddrin_2k<12> | -2.000 | 6.500 |
cpuaddrin_2k<13> | -2.000 | 6.500 |
cpuaddrin_2k<14> | -2.000 | 6.500 |
cpuaddrin_2k<15> | -2.000 | 6.500 |
cpuaddrin_64k<16> | -2.000 | 6.500 |
cpuaddrin_64k<17> | -2.000 | 6.500 |
cpuaddrin_64k<18> | -2.000 | 6.500 |
cpuaddrin_64k<19> | -2.000 | 6.500 |
cpuaddrin_64k<20> | -2.000 | 6.500 |
cpuaddrin_64k<21> | -2.000 | 6.500 |
cpuaddrin_64k<22> | -2.000 | 6.500 |
cpuaddrin_64k<23> | -2.000 | 6.500 |
cpurnw | -3.000 | 7.500 |
reset | -20.000 | 24.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
phi0 | 8.000 | 0.000 |
reset | 26.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | 14.000 | 7.500 |
cpuaddrin_16<0> | 14.000 | 7.500 |
cpuaddrin_16<1> | 14.000 | 7.500 |
cpuaddrin_16<2> | 14.000 | 7.500 |
cpuaddrin_16<3> | 14.000 | 7.500 |
cpuaddrin_2k<11> | 14.000 | 7.500 |
cpuaddrin_2k<12> | 14.000 | 7.500 |
cpuaddrin_2k<13> | 14.000 | 7.500 |
cpuaddrin_2k<14> | 14.000 | 7.500 |
cpuaddrin_2k<15> | 14.000 | 7.500 |
cpuaddrin_64k<16> | 14.000 | 7.500 |
cpuaddrin_64k<17> | 14.000 | 7.500 |
cpuaddrin_64k<18> | 14.000 | 7.500 |
cpuaddrin_64k<19> | 14.000 | 7.500 |
cpuaddrin_64k<20> | 14.000 | 7.500 |
cpuaddrin_64k<21> | 14.000 | 7.500 |
cpuaddrin_64k<22> | 14.000 | 7.500 |
cpuaddrin_64k<23> | 14.000 | 7.500 |
cpudata<0> | -20.000 | 24.500 |
cpudata<1> | -20.000 | 24.500 |
cpudata<2> | -20.000 | 24.500 |
cpudata<3> | -20.000 | 24.500 |
cpudata<4> | -20.000 | 24.500 |
cpudata<5> | -20.000 | 24.500 |
cpudata<6> | -20.000 | 24.500 |
cpudata<7> | -20.000 | 24.500 |
cpurnw | 14.000 | 7.500 |
cpuvda | -19.000 | 23.500 |
cpuvpa | -19.000 | 23.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | 14.000 | 7.500 |
cpuaddrin_16<0> | 14.000 | 7.500 |
cpuaddrin_16<1> | 14.000 | 7.500 |
cpuaddrin_16<2> | 14.000 | 7.500 |
cpuaddrin_16<3> | 14.000 | 7.500 |
cpuaddrin_2k<11> | 14.000 | 7.500 |
cpuaddrin_2k<12> | 14.000 | 7.500 |
cpuaddrin_2k<13> | 14.000 | 7.500 |
cpuaddrin_2k<14> | 14.000 | 7.500 |
cpuaddrin_2k<15> | 14.000 | 7.500 |
cpuaddrin_64k<16> | 14.000 | 7.500 |
cpuaddrin_64k<17> | 14.000 | 7.500 |
cpuaddrin_64k<18> | 14.000 | 7.500 |
cpuaddrin_64k<19> | 14.000 | 7.500 |
cpuaddrin_64k<20> | 14.000 | 7.500 |
cpuaddrin_64k<21> | 14.000 | 7.500 |
cpuaddrin_64k<22> | 14.000 | 7.500 |
cpuaddrin_64k<23> | 14.000 | 7.500 |
cpudata<0> | -20.000 | 24.500 |
cpudata<1> | -20.000 | 24.500 |
cpudata<2> | -20.000 | 24.500 |
cpudata<3> | -20.000 | 24.500 |
cpudata<4> | -20.000 | 24.500 |
cpudata<5> | -20.000 | 24.500 |
cpudata<6> | -20.000 | 24.500 |
cpudata<7> | -20.000 | 24.500 |
cpurnw | 14.000 | 7.500 |
cpuvda | -19.000 | 23.500 |
cpuvpa | -19.000 | 23.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | 14.000 | 7.500 |
cpuaddrin_16<0> | 14.000 | 7.500 |
cpuaddrin_16<1> | 14.000 | 7.500 |
cpuaddrin_16<2> | 14.000 | 7.500 |
cpuaddrin_16<3> | 14.000 | 7.500 |
cpuaddrin_2k<11> | 14.000 | 7.500 |
cpuaddrin_2k<12> | 14.000 | 7.500 |
cpuaddrin_2k<13> | 14.000 | 7.500 |
cpuaddrin_2k<14> | 14.000 | 7.500 |
cpuaddrin_2k<15> | 14.000 | 7.500 |
cpuaddrin_64k<16> | 14.000 | 7.500 |
cpuaddrin_64k<17> | 14.000 | 7.500 |
cpuaddrin_64k<18> | 14.000 | 7.500 |
cpuaddrin_64k<19> | 14.000 | 7.500 |
cpuaddrin_64k<20> | 14.000 | 7.500 |
cpuaddrin_64k<21> | 14.000 | 7.500 |
cpuaddrin_64k<22> | 14.000 | 7.500 |
cpuaddrin_64k<23> | 14.000 | 7.500 |
cpudata<0> | -20.000 | 24.500 |
cpudata<1> | -20.000 | 24.500 |
cpudata<2> | -20.000 | 24.500 |
cpudata<3> | -20.000 | 24.500 |
cpudata<4> | -20.000 | 24.500 |
cpudata<5> | -20.000 | 24.500 |
cpudata<6> | -20.000 | 24.500 |
cpudata<7> | -20.000 | 24.500 |
cpurnw | 14.000 | 7.500 |
cpuvda | -19.000 | 23.500 |
cpuvpa | -19.000 | 23.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
nramcs<0> | 167.000 |
nromcs | 166.000 |
nramcs<1> | 152.000 |
nromwe | 152.000 |
cpuclk | 135.000 |
latchen | 118.000 |
nslowbusclr | 70.000 |
rnw | 70.000 |
slowaddrlatch | 70.000 |
nslowdataenout | 8.000 |
Source | Destination | Delay |
---|---|---|
MyClock/phi0D9.Q | MyClock/phi0DA.D | 18.000 |
MyClock/phi0DA.Q | MyClock/phi0DB.D | 18.000 |
MyClock/phi0DB.Q | MyClock/phi0DC.D | 18.000 |
MyClock/phi0DC.Q | MyClock/phi0DD.D | 18.000 |
Source | Destination | Delay |
---|---|---|
MyClockSync/slowdone.Q | MyClockSync/slowdone.D | 18.000 |
Source | Destination | Delay |
---|---|---|
nslowdataen.Q | nslowdataen.D | 18.000 |
Source | Destination | Delay |
---|---|---|
nslowdataen.Q | nslowdataen.D | 18.000 |
Source | Destination | Delay |
---|---|---|
nslowdataen.Q | nslowdataen.D | 18.000 |
Source | Destination | Delay |
---|---|---|
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<1>.D | 52.000 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<2>.D | 52.000 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<3>.D | 52.000 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<1>.D | 52.000 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<2>.D | 52.000 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<3>.D | 52.000 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<1>.D | 52.000 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<2>.D | 52.000 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<3>.D | 52.000 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<1>.D | 52.000 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<2>.D | 52.000 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<3>.D | 52.000 |
masterclk.Q | Mytiming/clkcounter<1>.D | 52.000 |
masterclk.Q | Mytiming/clkcounter<2>.D | 52.000 |
masterclk.Q | Mytiming/clkcounter<3>.D | 52.000 |
Mytiming/clkcounter<0>.Q | masterclk.D | 35.000 |
Mytiming/clkcounter<1>.Q | masterclk.D | 35.000 |
Mytiming/clkcounter<2>.Q | masterclk.D | 35.000 |
Mytiming/clkcounter<3>.Q | masterclk.D | 35.000 |
masterclk.Q | masterclk.D | 35.000 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<0>.D | 19.000 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<0>.D | 19.000 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<0>.D | 19.000 |
masterclk.Q | Mytiming/clkcounter<0>.D | 19.000 |
MyClock/phi0D1.Q | MyClock/phi0D2.D | 18.000 |
MyClock/phi0D2.Q | MyClock/phi0D3.D | 18.000 |
MyClock/phi0D3.Q | MyClock/phi0D4.D | 18.000 |
MyClock/phi0D4.Q | MyClock/phi0D5.D | 18.000 |
MyClock/phi0D5.Q | MyClock/phi0D6.D | 18.000 |
MyClock/phi0D6.Q | MyClock/phi0D7.D | 18.000 |
MyClock/phi0D7.Q | MyClock/phi0D8.D | 18.000 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<0>.D | 18.000 |
Source | Destination | Delay |
---|---|---|
bootrom.Q | slowdetected.D | 36.000 |
fastvread.Q | slowdetected.D | 36.000 |
slow64k.Q | slowdetected.D | 36.000 |
hidebogus.Q | slowdetected.D | 19.000 |
useslowclk.Q | slowdetected.D | 19.000 |
bootrom.Q | bootrom.D | 18.000 |
clklatch<0>.Q | clklatch<0>.D | 18.000 |
clklatch<1>.Q | clklatch<1>.D | 18.000 |
clklatch<2>.Q | clklatch<2>.D | 18.000 |
clklatch<3>.Q | clklatch<3>.D | 18.000 |
clklatch<4>.Q | clklatch<4>.D | 18.000 |
fastmode.Q | fastmode.D | 18.000 |
fastvread.Q | fastvread.D | 18.000 |
hidebogus.Q | hidebogus.D | 18.000 |
prgrom.Q | prgrom.D | 18.000 |
slow64k.Q | slow64k.D | 18.000 |
useslowclk.Q | useslowclk.D | 18.000 |
wprotect<0>.Q | wprotect<0>.D | 18.000 |
wprotect<1>.Q | wprotect<1>.D | 18.000 |
Source | Destination | Delay |
---|---|---|
bootrom.Q | slowdetected.D | 36.000 |
fastvread.Q | slowdetected.D | 36.000 |
slow64k.Q | slowdetected.D | 36.000 |
hidebogus.Q | slowdetected.D | 19.000 |
useslowclk.Q | slowdetected.D | 19.000 |
bootrom.Q | bootrom.D | 18.000 |
clklatch<0>.Q | clklatch<0>.D | 18.000 |
clklatch<1>.Q | clklatch<1>.D | 18.000 |
clklatch<2>.Q | clklatch<2>.D | 18.000 |
clklatch<3>.Q | clklatch<3>.D | 18.000 |
clklatch<4>.Q | clklatch<4>.D | 18.000 |
fastmode.Q | fastmode.D | 18.000 |
fastvread.Q | fastvread.D | 18.000 |
hidebogus.Q | hidebogus.D | 18.000 |
prgrom.Q | prgrom.D | 18.000 |
slow64k.Q | slow64k.D | 18.000 |
useslowclk.Q | useslowclk.D | 18.000 |
wprotect<0>.Q | wprotect<0>.D | 18.000 |
wprotect<1>.Q | wprotect<1>.D | 18.000 |
Source | Destination | Delay |
---|---|---|
bootrom.Q | slowdetected.D | 36.000 |
fastvread.Q | slowdetected.D | 36.000 |
slow64k.Q | slowdetected.D | 36.000 |
hidebogus.Q | slowdetected.D | 19.000 |
useslowclk.Q | slowdetected.D | 19.000 |
bootrom.Q | bootrom.D | 18.000 |
clklatch<0>.Q | clklatch<0>.D | 18.000 |
clklatch<1>.Q | clklatch<1>.D | 18.000 |
clklatch<2>.Q | clklatch<2>.D | 18.000 |
clklatch<3>.Q | clklatch<3>.D | 18.000 |
clklatch<4>.Q | clklatch<4>.D | 18.000 |
fastmode.Q | fastmode.D | 18.000 |
fastvread.Q | fastvread.D | 18.000 |
hidebogus.Q | hidebogus.D | 18.000 |
prgrom.Q | prgrom.D | 18.000 |
slow64k.Q | slow64k.D | 18.000 |
useslowclk.Q | useslowclk.D | 18.000 |
wprotect<0>.Q | wprotect<0>.D | 18.000 |
wprotect<1>.Q | wprotect<1>.D | 18.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
cpuaddr_ismyio | nramcs<0> | 34.000 |
cpuaddrin_16<2> | nramcs<0> | 34.000 |
cpuaddrin_16<3> | nramcs<0> | 34.000 |
cpuaddrin_2k<11> | nramcs<0> | 34.000 |
cpuaddrin_2k<12> | nramcs<0> | 34.000 |
cpuaddrin_2k<13> | nramcs<0> | 34.000 |
cpuaddrin_2k<14> | nramcs<0> | 34.000 |
cpuaddrin_2k<15> | nramcs<0> | 34.000 |
cpuaddrin_64k<16> | nramcs<0> | 34.000 |
cpuaddrin_64k<17> | nramcs<0> | 34.000 |
cpuaddrin_64k<18> | nramcs<0> | 34.000 |
cpuaddrin_64k<19> | nramcs<0> | 34.000 |
cpuaddrin_64k<20> | nramcs<0> | 34.000 |
cpuaddrin_64k<21> | nramcs<0> | 34.000 |
cpuaddrin_64k<22> | nramcs<0> | 34.000 |
cpuaddrin_64k<23> | nramcs<0> | 34.000 |
cpuaddr_ismyio | nromcs | 33.000 |
cpuaddrin_16<1> | nramcs<0> | 33.000 |
cpuaddrin_16<2> | nromcs | 33.000 |
cpuaddrin_16<3> | nromcs | 33.000 |
cpuaddrin_2k<11> | nromcs | 33.000 |
cpuaddrin_2k<12> | nromcs | 33.000 |
cpuaddrin_2k<13> | nromcs | 33.000 |
cpuaddrin_2k<14> | nromcs | 33.000 |
cpuaddrin_2k<15> | nromcs | 33.000 |
cpuaddrin_64k<16> | nromcs | 33.000 |
cpuaddrin_64k<17> | nromcs | 33.000 |
cpuaddrin_64k<18> | nromcs | 33.000 |
cpuaddrin_64k<19> | nromcs | 33.000 |
cpuaddrin_64k<20> | nromcs | 33.000 |
cpuaddrin_64k<21> | nromcs | 33.000 |
cpuaddrin_64k<22> | nromcs | 33.000 |
cpuaddrin_64k<23> | nromcs | 33.000 |
cpurnw | nramcs<0> | 33.000 |
cpuvda | nramcs<0> | 33.000 |
cpuvpa | nramcs<0> | 33.000 |
reset | nramcs<0> | 33.000 |
cpuaddrin_16<1> | nromcs | 32.000 |
cpurnw | nromcs | 32.000 |
cpuvda | nramcs<1> | 32.000 |
cpuvda | nromcs | 32.000 |
cpuvda | nromwe | 32.000 |
cpuvpa | nramcs<1> | 32.000 |
cpuvpa | nromcs | 32.000 |
cpuvpa | nromwe | 32.000 |
reset | nramcs<1> | 32.000 |
reset | nromcs | 32.000 |
reset | nromwe | 32.000 |
cpuaddrin_64k<19> | nramcs<1> | 15.000 |
cpuaddrin_64k<19> | nromwe | 15.000 |
cpuaddrin_64k<20> | nramcs<1> | 15.000 |
cpuaddrin_64k<20> | nromwe | 15.000 |
cpuaddrin_64k<21> | nramcs<1> | 15.000 |
cpuaddrin_64k<21> | nromwe | 15.000 |
cpuaddrin_64k<22> | nramcs<1> | 15.000 |
cpuaddrin_64k<22> | nromwe | 15.000 |
cpuaddrin_64k<23> | nramcs<1> | 15.000 |
cpuaddrin_64k<23> | nromwe | 15.000 |
cpurnw | cpuwnr | 15.000 |
cpurnw | nromwe | 15.000 |
phi0 | nromcs | 15.000 |
phi0 | phi1 | 15.000 |
phi0 | phi2 | 15.000 |