cpldfit: version L.33 Xilinx Inc. Fitter Report Design Name: PET816 Date: 8-11-2010, 11:28PM Device Used: XC95108-15-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 67 /108 ( 62%) 189 /540 ( 35%) 137/216 ( 63%) 42 /108 ( 39%) 47 /69 ( 68%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 16/18 21/36 21 44/90 3/12 FB2 16/18 19/36 19 22/90 1/12 FB3 16/18 31/36 31 64/90 2/12 FB4 1/18 2/36 2 1/90 0/11 FB5 9/18 32/36 32 32/90 4/11 FB6 9/18 32/36 32 26/90 3/11 ----- ----- ----- ----- 67/108 137/216 189/540 13/69 * - Resource is exhausted ** Global Control Resources ** The complement of 'fastclkin' mapped onto global clock net GCK1. Signal 'fastclkin' mapped onto global clock net GCK2. The complement of 'phi0' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 32 32 | I/O : 44 63 Output : 13 13 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 2 2 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 47 47 ** Power Data ** There are 67 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'fastclkin' based upon the LOC constraint 'P10'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'phi0' based upon the LOC constraint 'P9'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'auxconf'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 13 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State cpuclk 1 1 FB1_9 6 I/O O STD FAST nslowdataenout 2 2 FB1_11 7 I/O O STD FAST RESET phi2 1 1 FB1_16 12 GCK/I/O O STD FAST cpuwnr 1 1 FB2_11 79 I/O O STD FAST slowaddrlatch 4 5 FB3_9 20 I/O O STD FAST RESET phi1 1 1 FB3_12 23 I/O O STD FAST nslowbusclr 3 4 FB5_2 32 I/O O STD FAST RESET rnw 3 5 FB5_3 33 I/O O STD FAST RESET nramcs<0> 10 17 FB5_14 41 I/O O STD FAST nramcs<1> 1 6 FB5_15 43 I/O O STD FAST nromwe 1 7 FB6_8 50 I/O O STD FAST latchen 1 3 FB6_11 52 I/O O STD FAST nromcs 3 15 FB6_12 53 I/O O STD FAST ** 54 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State Mytiming/clkcounter<0> 7 8 FB1_1 STD SET Mytiming/clkcounter<2> 8 7 FB1_2 STD SET MyClock/phi0D3 1 1 FB1_5 STD RESET MyClock/phi0D2 1 1 FB1_6 STD RESET MyClock/phi0D1 1 1 FB1_7 STD RESET $OpTx$FX_DC$98 1 5 FB1_8 STD $OpTx$FX_DC$97 1 4 FB1_10 STD masterclk 2 2 FB1_12 STD RESET BUF_masterclk 2 5 FB1_13 STD Mytiming/clkcounter<3> 7 7 FB1_14 STD SET Mytiming/clkcounter<1> 7 10 FB1_15 STD SET masterclk/masterclk_RSTF 1 2 FB1_17 STD fastclkby2 1 1 FB1_18 STD RESET clklatchx<3>/clklatchx<3>_D2 1 2 FB2_3 STD clklatchx<2>/clklatchx<2>_D2 1 2 FB2_4 STD clklatchx<1>/clklatchx<1>_D2 1 2 FB2_5 STD clklatchx<0>/clklatchx<0>_D2 1 2 FB2_6 STD MyClock/phi0D8 1 1 FB2_7 STD RESET MyClock/phi0D7 1 1 FB2_8 STD RESET MyClock/phi0D6 1 1 FB2_9 STD RESET MyClock/phi0D5 1 1 FB2_10 STD RESET MyClock/phi0D4 1 1 FB2_12 STD RESET nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF 2 3 FB2_13 STD MyClock/phi0DD 2 2 FB2_14 STD RESET MyClock/phi0DC 2 2 FB2_15 STD RESET MyClock/phi0DB 2 2 FB2_16 STD RESET MyClock/phi0DA 2 2 FB2_17 STD RESET MyClock/phi0D9 2 2 FB2_18 STD RESET slowaccess 3 3 FB3_3 STD RESET wprotect<1> 4 5 FB3_4 STD RESET wprotect<0> 4 5 FB3_5 STD RESET useslowclk 4 5 FB3_6 STD RESET slow64k 4 5 FB3_7 STD RESET prgrom 4 5 FB3_8 STD RESET fastvread 4 5 FB3_10 STD RESET fastmode 4 5 FB3_11 STD RESET clklatch<3> 4 5 FB3_13 STD RESET clklatch<2> 4 5 FB3_14 STD RESET clklatch<4> 5 7 FB3_15 STD RESET clklatch<1> 5 7 FB3_16 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State clklatch<0> 5 7 FB3_17 STD RESET bootrom 5 6 FB3_18 STD RESET clklatchx<4>/clklatchx<4>_D2 1 2 FB4_18 STD MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 1 19 FB5_12 STD MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 1 19 FB5_13 STD slowaccess/slowaccess_RSTF 2 4 FB5_16 STD clkenable 3 4 FB5_17 STD RESET isorig/isorig_D2 8 21 FB5_18 STD slowdetected/slowdetected_RSTF 1 2 FB6_13 STD $OpTx$FX_DC$91 2 4 FB6_14 STD MyClockSync/slowdone 3 6 FB6_15 STD RESET nslowdataen 4 7 FB6_16 STD RESET hidebogus 4 5 FB6_17 STD RESET slowdetected 7 11 FB6_18 STD RESET ** 34 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use cpuaddrin_2k<12> FB1_2 1 I/O I cpuaddrin_2k<13> FB1_3 2 I/O I cpuaddrin_2k<14> FB1_5 3 I/O I cpuaddrin_2k<15> FB1_6 4 I/O I cpuaddrin_2k<11> FB1_8 5 I/O I phi0 FB1_12 9 GCK/I/O GCK/I fastclkin FB1_14 10 GCK/I/O GCK cpuvpa FB1_15 11 I/O I cpuvda FB1_17 13 I/O I cpuaddrin_64k<16> FB2_2 71 I/O I cpuaddrin_64k<17> FB2_3 72 I/O I cpuaddrin_64k<18> FB2_6 75 I/O I cpuaddrin_16<1> FB2_14 81 I/O I cpuaddrin_16<0> FB2_15 82 I/O I cpuaddrin_16<3> FB2_16 83 I/O I cpuaddrin_16<2> FB2_17 84 I/O I cpurnw FB3_5 17 I/O I reset FB3_6 18 I/O I bootromin FB3_8 19 I/O I cpuaddr_ismyio FB3_15 25 I/O I cpudata<2> FB4_2 57 I/O I cpudata<4> FB4_3 58 I/O I cpudata<6> FB4_5 61 I/O I cpudata<7> FB4_6 62 I/O I cpudata<5> FB4_8 63 I/O I cpuaddrin_64k<23> FB4_11 66 I/O I cpuaddrin_64k<22> FB4_12 67 I/O I cpuaddrin_64k<21> FB4_14 68 I/O I cpuaddrin_64k<20> FB4_15 69 I/O I cpuaddrin_64k<19> FB4_17 70 I/O I rdy FB5_11 39 I/O I cpudata<1> FB6_14 54 I/O I cpudata<0> FB6_15 55 I/O I cpudata<3> FB6_17 56 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 21/15 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use Mytiming/clkcounter<0> 7 2<- 0 0 FB1_1 (b) (b) Mytiming/clkcounter<2> 8 3<- 0 0 FB1_2 1 I/O I (unused) 0 0 /\3 2 FB1_3 2 I/O I (unused) 0 0 0 5 FB1_4 (b) MyClock/phi0D3 1 0 0 4 FB1_5 3 I/O I MyClock/phi0D2 1 0 0 4 FB1_6 4 I/O I MyClock/phi0D1 1 0 0 4 FB1_7 (b) (b) $OpTx$FX_DC$98 1 0 0 4 FB1_8 5 I/O I cpuclk 1 0 0 4 FB1_9 6 I/O O $OpTx$FX_DC$97 1 0 0 4 FB1_10 (b) (b) nslowdataenout 2 0 0 3 FB1_11 7 I/O O masterclk 2 0 0 3 FB1_12 9 GCK/I/O GCK/I BUF_masterclk 2 0 \/2 1 FB1_13 (b) (b) Mytiming/clkcounter<3> 7 2<- 0 0 FB1_14 10 GCK/I/O GCK Mytiming/clkcounter<1> 7 2<- 0 0 FB1_15 11 I/O I phi2 1 0 /\2 2 FB1_16 12 GCK/I/O O masterclk/masterclk_RSTF 1 0 0 4 FB1_17 13 I/O I fastclkby2 1 0 \/2 2 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$97 8: Mytiming/clkcounter<2> 15: clklatchx<4>/clklatchx<4>_D2 2: $OpTx$FX_DC$98 9: Mytiming/clkcounter<3> 16: latchen 3: BUF_masterclk 10: clkenable 17: masterclk 4: MyClock/phi0D1 11: clklatchx<0>/clklatchx<0>_D2 18: masterclk/masterclk_RSTF 5: MyClock/phi0D2 12: clklatchx<1>/clklatchx<1>_D2 19: nslowdataen 6: Mytiming/clkcounter<0> 13: clklatchx<2>/clklatchx<2>_D2 20: phi0 7: Mytiming/clkcounter<1> 14: clklatchx<3>/clklatchx<3>_D2 21: reset Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs Mytiming/clkcounter<0> .....XXXX.XX....XX...................... 8 8 Mytiming/clkcounter<2> X....XXXX....X...X...................... 7 7 MyClock/phi0D3 ....X................................... 1 1 MyClock/phi0D2 ...X.................................... 1 1 MyClock/phi0D1 ...................X.................... 1 1 $OpTx$FX_DC$98 ..X.......XXXX.......................... 5 5 cpuclk ...............X........................ 1 1 $OpTx$FX_DC$97 ..X.......XXX........................... 4 4 nslowdataenout ..................X.X................... 2 2 masterclk ..X..............X...................... 2 2 BUF_masterclk .....XXXX.......X....................... 5 5 Mytiming/clkcounter<3> .X...XXXX.....X..X...................... 7 7 Mytiming/clkcounter<1> X.X..XXXX.XXX....X...................... 10 10 phi2 ...................X.................... 1 1 masterclk/masterclk_RSTF .........X..........X................... 2 2 fastclkby2 ....................X................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 19/17 Number of signals used by logic mapping into function block: 19 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 71 I/O I clklatchx<3>/clklatchx<3>_D2 1 0 0 4 FB2_3 72 I/O I clklatchx<2>/clklatchx<2>_D2 1 0 0 4 FB2_4 (b) (b) clklatchx<1>/clklatchx<1>_D2 1 0 0 4 FB2_5 74 GSR/I/O (b) clklatchx<0>/clklatchx<0>_D2 1 0 0 4 FB2_6 75 I/O I MyClock/phi0D8 1 0 0 4 FB2_7 (b) (b) MyClock/phi0D7 1 0 0 4 FB2_8 76 GTS/I/O (b) MyClock/phi0D6 1 0 0 4 FB2_9 77 GTS/I/O (b) MyClock/phi0D5 1 0 0 4 FB2_10 (b) (b) cpuwnr 1 0 0 4 FB2_11 79 I/O O MyClock/phi0D4 1 0 0 4 FB2_12 80 I/O (b) nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF 2 0 0 3 FB2_13 (b) (b) MyClock/phi0DD 2 0 0 3 FB2_14 81 I/O I MyClock/phi0DC 2 0 0 3 FB2_15 82 I/O I MyClock/phi0DB 2 0 0 3 FB2_16 83 I/O I MyClock/phi0DA 2 0 0 3 FB2_17 84 I/O I MyClock/phi0D9 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: MyClock/phi0D3 8: MyClock/phi0DA 14: clklatch<2> 2: MyClock/phi0D4 9: MyClock/phi0DB 15: clklatch<3> 3: MyClock/phi0D5 10: MyClock/phi0DC 16: cpurnw 4: MyClock/phi0D6 11: MyClock/phi0DD 17: fastclkby2 5: MyClock/phi0D7 12: clklatch<0> 18: fastmode 6: MyClock/phi0D8 13: clklatch<1> 19: useslowclk 7: MyClock/phi0D9 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs clklatchx<3>/clklatchx<3>_D2 ..............X...X..................... 2 2 clklatchx<2>/clklatchx<2>_D2 .............X....X..................... 2 2 clklatchx<1>/clklatchx<1>_D2 ............X.....X..................... 2 2 clklatchx<0>/clklatchx<0>_D2 ...........X......X..................... 2 2 MyClock/phi0D8 ....X................................... 1 1 MyClock/phi0D7 ...X.................................... 1 1 MyClock/phi0D6 ..X..................................... 1 1 MyClock/phi0D5 .X...................................... 1 1 cpuwnr ...............X........................ 1 1 MyClock/phi0D4 X....................................... 1 1 nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF ....X.....X......X...................... 3 3 MyClock/phi0DD .........X......X....................... 2 2 MyClock/phi0DC ........X.......X....................... 2 2 MyClock/phi0DB .......X........X....................... 2 2 MyClock/phi0DA ......X.........X....................... 2 2 MyClock/phi0D9 .....X..........X....................... 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 31/5 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O slowaccess 3 0 0 2 FB3_3 15 I/O (b) wprotect<1> 4 0 0 1 FB3_4 (b) (b) wprotect<0> 4 0 0 1 FB3_5 17 I/O I useslowclk 4 0 0 1 FB3_6 18 I/O I slow64k 4 0 0 1 FB3_7 (b) (b) prgrom 4 0 0 1 FB3_8 19 I/O I slowaddrlatch 4 0 0 1 FB3_9 20 I/O O fastvread 4 0 0 1 FB3_10 (b) (b) fastmode 4 0 0 1 FB3_11 21 I/O (b) phi1 1 0 0 4 FB3_12 23 I/O O clklatch<3> 4 0 0 1 FB3_13 (b) (b) clklatch<2> 4 0 0 1 FB3_14 24 I/O (b) clklatch<4> 5 0 0 0 FB3_15 25 I/O I clklatch<1> 5 0 0 0 FB3_16 26 I/O (b) clklatch<0> 5 0 0 0 FB3_17 31 I/O (b) bootrom 5 0 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 12: cpudata<2> 22: nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF 2: MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 13: cpudata<3> 23: phi0 3: bootrom 14: cpudata<4> 24: prgrom 4: bootromin 15: cpudata<5> 25: reset 5: clklatch<0> 16: cpudata<6> 26: slow64k 6: clklatch<1> 17: cpudata<7> 27: slowaccess/slowaccess_RSTF 7: clklatch<2> 18: fastmode 28: slowdetected 8: clklatch<3> 19: fastvread 29: useslowclk 9: clklatch<4> 20: isorig/isorig_D2 30: wprotect<0> 10: cpudata<0> 21: latchen 31: wprotect<1> 11: cpudata<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs slowaccess .....................X....XX............ 3 3 wprotect<1> X.........X.........X...X.....X......... 5 5 wprotect<0> X........X..........X...X....X.......... 5 5 useslowclk X............X......X...X...X........... 5 5 slow64k X.............X.....X...XX.............. 5 5 prgrom X...............X...X..XX............... 5 5 slowaddrlatch ...................X.X..X.XX............ 5 5 fastvread X..........X......X.X...X............... 5 5 fastmode .X..............XX..X...X............... 5 5 phi1 ......................X................. 1 1 clklatch<3> .X.....X....X.......X...X............... 5 5 clklatch<2> .X....X....X........X...X............... 5 5 clklatch<4> .X......X..XXX......X...X............... 7 7 clklatch<1> .X...X....XXX.......X...X............... 7 7 clklatch<0> .X..X....X.XX.......X...X............... 7 7 bootrom X.XX...........X....X...X............... 6 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 2/34 Number of signals used by logic mapping into function block: 2 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 57 I/O I (unused) 0 0 0 5 FB4_3 58 I/O I (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 61 I/O I (unused) 0 0 0 5 FB4_6 62 I/O I (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 63 I/O I (unused) 0 0 0 5 FB4_9 65 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 66 I/O I (unused) 0 0 0 5 FB4_12 67 I/O I (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 68 I/O I (unused) 0 0 0 5 FB4_15 69 I/O I (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 70 I/O I clklatchx<4>/clklatchx<4>_D2 1 0 0 4 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: clklatch<4> 2: useslowclk Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs clklatchx<4>/clklatchx<4>_D2 XX...................................... 2 2 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\2 3 FB5_1 (b) (b) nslowbusclr 3 0 0 2 FB5_2 32 I/O O rnw 3 0 0 2 FB5_3 33 I/O O (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 34 I/O (unused) 0 0 0 5 FB5_6 35 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 36 I/O (unused) 0 0 0 5 FB5_9 37 I/O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 39 I/O I MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 1 0 0 4 FB5_12 40 I/O (b) MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 1 0 \/2 2 FB5_13 (b) (b) nramcs<0> 10 5<- 0 0 FB5_14 41 I/O O nramcs<1> 1 0 /\3 1 FB5_15 43 I/O O slowaccess/slowaccess_RSTF 2 0 0 3 FB5_16 (b) (b) clkenable 3 0 \/1 1 FB5_17 44 I/O (b) isorig/isorig_D2 8 3<- 0 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$91 12: cpuaddrin_2k<12> 23: cpuaddrin_64k<23> 2: MyClock/phi0D2 13: cpuaddrin_2k<13> 24: cpurnw 3: MyClock/phi0D3 14: cpuaddrin_2k<14> 25: fastvread 4: MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 15: cpuaddrin_2k<15> 26: isorig/isorig_D2 5: bootrom 16: cpuaddrin_64k<16> 27: nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF 6: cpuaddr_ismyio 17: cpuaddrin_64k<17> 28: reset 7: cpuaddrin_16<0> 18: cpuaddrin_64k<18> 29: slow64k 8: cpuaddrin_16<1> 19: cpuaddrin_64k<19> 30: slowdetected 9: cpuaddrin_16<2> 20: cpuaddrin_64k<20> 31: wprotect<0> 10: cpuaddrin_16<3> 21: cpuaddrin_64k<21> 32: wprotect<1> 11: cpuaddrin_2k<11> 22: cpuaddrin_64k<22> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs nslowbusclr .........................XXX.X.......... 4 4 rnw .......................X.XXX.X.......... 5 5 MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 .....XXXXXXXXXXXXXXXXXXX................ 19 19 MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 ...X.X.XXXXXXXXXXXXXXXXX................ 19 19 nramcs<0> X...X.......XXXXXXXXXXXX.X....XX........ 17 17 nramcs<1> X.................XXXXX................. 6 6 slowaccess/slowaccess_RSTF .XX........................X.X.......... 4 4 clkenable .XX........................X.X.......... 4 4 isorig/isorig_D2 ....XX.XXXXXXXXXXXXXXXXXX...X........... 21 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\1 4 FB6_1 (b) (b) (unused) 0 0 0 5 FB6_2 45 I/O (unused) 0 0 0 5 FB6_3 46 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 47 I/O (unused) 0 0 0 5 FB6_6 48 I/O (unused) 0 0 0 5 FB6_7 (b) nromwe 1 0 0 4 FB6_8 50 I/O O (unused) 0 0 0 5 FB6_9 51 I/O (unused) 0 0 0 5 FB6_10 (b) latchen 1 0 0 4 FB6_11 52 I/O O nromcs 3 0 0 2 FB6_12 53 I/O O slowdetected/slowdetected_RSTF 1 0 0 4 FB6_13 (b) (b) $OpTx$FX_DC$91 2 0 0 3 FB6_14 54 I/O I MyClockSync/slowdone 3 0 0 2 FB6_15 55 I/O I nslowdataen 4 0 0 1 FB6_16 (b) (b) hidebogus 4 0 \/1 0 FB6_17 56 I/O I slowdetected 7 2<- 0 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$91 12: cpuaddrin_64k<21> 23: nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF 2: MyClock/phi0D2 13: cpuaddrin_64k<22> 24: nslowdataen 3: MyClock/phi0D3 14: cpuaddrin_64k<23> 25: phi0 4: MyClockSync/slowdone 15: cpudata<3> 26: prgrom 5: MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 16: cpurnw 27: rdy 6: bootrom 17: cpuvda 28: reset 7: cpuaddrin_64k<16> 18: cpuvpa 29: slowaccess 8: cpuaddrin_64k<17> 19: hidebogus 30: slowdetected 9: cpuaddrin_64k<18> 20: isorig/isorig_D2 31: slowdetected/slowdetected_RSTF 10: cpuaddrin_64k<19> 21: latchen 32: useslowclk 11: cpuaddrin_64k<20> 22: masterclk Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs nromwe X........XXXXX.X........................ 7 7 latchen .....................X......XX.......... 3 3 nromcs X....XXXXXXXXX.X...X....XX..X........... 15 15 slowdetected/slowdetected_RSTF ...X.......................X............ 2 2 $OpTx$FX_DC$91 ................XX..X......X............ 4 4 MyClockSync/slowdone .XXX......................X.XX.......... 6 6 nslowdataen .XX................X..XX...X.X.......... 7 7 hidebogus ....X.........X...X.X......X............ 5 5 slowdetected ..........XXXX..XXXXX.........XX........ 11 11 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$91 <= ((reset AND cpuvpa AND NOT latchen) OR (reset AND cpuvda AND NOT latchen)); $OpTx$FX_DC$97 <= (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT clklatchx(0)/clklatchx(0)_D2 AND clklatchx(2)/clklatchx(2)_D2 AND NOT BUF_masterclk); $OpTx$FX_DC$98 <= (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT clklatchx(0)/clklatchx(0)_D2 AND clklatchx(2)/clklatchx(2)_D2 AND NOT BUF_masterclk AND NOT clklatchx(3)/clklatchx(3)_D2); BUF_masterclk <= masterclk XOR BUF_masterclk <= (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3)); FDCPE_MyClock/phi0D1: FDCPE port map (MyClock/phi0D1,phi0,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D2: FDCPE port map (MyClock/phi0D2,MyClock/phi0D1,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D3: FDCPE port map (MyClock/phi0D3,MyClock/phi0D2,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D4: FDCPE port map (MyClock/phi0D4,MyClock/phi0D3,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D5: FDCPE port map (MyClock/phi0D5,MyClock/phi0D4,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D6: FDCPE port map (MyClock/phi0D6,MyClock/phi0D5,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D7: FDCPE port map (MyClock/phi0D7,MyClock/phi0D6,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D8: FDCPE port map (MyClock/phi0D8,MyClock/phi0D7,NOT fastclkin,'0','0'); FDCPE_MyClock/phi0D9: FDCPE port map (MyClock/phi0D9,MyClock/phi0D8,fastclkby2,'0','0'); FDCPE_MyClock/phi0DA: FDCPE port map (MyClock/phi0DA,MyClock/phi0D9,fastclkby2,'0','0'); FDCPE_MyClock/phi0DB: FDCPE port map (MyClock/phi0DB,MyClock/phi0DA,fastclkby2,'0','0'); FDCPE_MyClock/phi0DC: FDCPE port map (MyClock/phi0DC,MyClock/phi0DB,fastclkby2,'0','0'); FDCPE_MyClock/phi0DD: FDCPE port map (MyClock/phi0DD,MyClock/phi0DC,fastclkby2,'0','0'); FDCPE_MyClockSync/slowdone: FDCPE port map (MyClockSync/slowdone,MyClockSync/slowdone_D,NOT phi0,MyClockSync/slowdone_CLR,'0'); MyClockSync/slowdone_D <= ((slowaccess AND rdy) OR (MyClockSync/slowdone AND NOT rdy)); MyClockSync/slowdone_CLR <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2); MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_16(0) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio); FDCPE_Mytiming/clkcounter0: FDCPE port map (Mytiming/clkcounter(0),Mytiming/clkcounter_D(0),NOT fastclkin,Mytiming/clkcounter_CLR(0),Mytiming/clkcounter_PRE(0)); Mytiming/clkcounter_D(0) <= ((NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT clklatchx(1)/clklatchx(1)_D2 AND clklatchx(0)/clklatchx(0)_D2) OR (NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND masterclk AND clklatchx(1)/clklatchx(1)_D2 AND masterclk/masterclk_RSTF AND NOT clklatchx(0)/clklatchx(0)_D2) OR (Mytiming/clkcounter(0) AND masterclk/masterclk_RSTF) OR (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT masterclk AND NOT clklatchx(1)/clklatchx(1)_D2)); Mytiming/clkcounter_CLR(0) <= (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF); Mytiming/clkcounter_PRE(0) <= (clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF); FDCPE_Mytiming/clkcounter1: FDCPE port map (Mytiming/clkcounter(1),Mytiming/clkcounter_D(1),NOT fastclkin,Mytiming/clkcounter_CLR(1),Mytiming/clkcounter_PRE(1)); Mytiming/clkcounter_D(1) <= ((Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(0) AND Mytiming/clkcounter(1) AND masterclk/masterclk_RSTF) OR (NOT masterclk/masterclk_RSTF AND clklatchx(2)/clklatchx(2)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND clklatchx(2)/clklatchx(2)_D2 AND NOT $OpTx$FX_DC$97) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT clklatchx(1)/clklatchx(1)_D2 AND masterclk/masterclk_RSTF AND NOT clklatchx(0)/clklatchx(0)_D2 AND NOT $OpTx$FX_DC$97 AND NOT BUF_masterclk)); Mytiming/clkcounter_CLR(1) <= (NOT masterclk/masterclk_RSTF AND clklatchx(2)/clklatchx(2)_D2); Mytiming/clkcounter_PRE(1) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(2)/clklatchx(2)_D2); FDCPE_Mytiming/clkcounter2: FDCPE port map (Mytiming/clkcounter(2),Mytiming/clkcounter_D(2),NOT fastclkin,Mytiming/clkcounter_CLR(2),Mytiming/clkcounter_PRE(2)); Mytiming/clkcounter_D(2) <= ((Mytiming/clkcounter(0) AND Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF) OR (Mytiming/clkcounter(1) AND Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND Mytiming/clkcounter(3) AND masterclk/masterclk_RSTF) OR (NOT masterclk/masterclk_RSTF AND clklatchx(3)/clklatchx(3)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT $OpTx$FX_DC$97 AND clklatchx(3)/clklatchx(3)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF AND $OpTx$FX_DC$97 AND NOT clklatchx(3)/clklatchx(3)_D2)); Mytiming/clkcounter_CLR(2) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(3)/clklatchx(3)_D2); Mytiming/clkcounter_PRE(2) <= (NOT masterclk/masterclk_RSTF AND clklatchx(3)/clklatchx(3)_D2); FTCPE_Mytiming/clkcounter3: FTCPE port map (Mytiming/clkcounter(3),Mytiming/clkcounter_T(3),NOT fastclkin,Mytiming/clkcounter_CLR(3),Mytiming/clkcounter_PRE(3)); Mytiming/clkcounter_T(3) <= ((Mytiming/clkcounter(3) AND NOT masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND Mytiming/clkcounter(3) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(3) AND NOT masterclk/masterclk_RSTF AND clklatchx(4)/clklatchx(4)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND clklatchx(4)/clklatchx(4)_D2 AND NOT $OpTx$FX_DC$98) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2 AND $OpTx$FX_DC$98)); Mytiming/clkcounter_CLR(3) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2); Mytiming/clkcounter_PRE(3) <= (NOT masterclk/masterclk_RSTF AND clklatchx(4)/clklatchx(4)_D2); FDCPE_bootrom: FDCPE port map (bootrom,bootrom_D,latchen,bootrom_CLR,bootrom_PRE); bootrom_D <= ((bootrom AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(6) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); bootrom_CLR <= (NOT reset AND NOT bootromin); bootrom_PRE <= (NOT reset AND bootromin); FDCPE_clkenable: FDCPE port map (clkenable,'1',clkenable_C,clkenable_CLR,NOT reset); clkenable_C <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); clkenable_CLR <= (reset AND slowdetected); FDCPE_clklatch0: FDCPE port map (clklatch(0),clklatch_D(0),latchen,'0',NOT reset); clklatch_D(0) <= ((NOT clklatch(0) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND NOT cpudata(0) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND NOT cpudata(0) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); FDCPE_clklatch1: FDCPE port map (clklatch(1),clklatch_D(1),latchen,'0',NOT reset); clklatch_D(1) <= ((NOT clklatch(1) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND NOT cpudata(1) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND NOT cpudata(1) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); FDCPE_clklatch2: FDCPE port map (clklatch(2),clklatch_D(2),latchen,'0',NOT reset); clklatch_D(2) <= ((clklatch(2) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); FDCPE_clklatch3: FDCPE port map (clklatch(3),clklatch_D(3),latchen,'0',NOT reset); clklatch_D(3) <= ((clklatch(3) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); FDCPE_clklatch4: FDCPE port map (clklatch(4),clklatch_D(4),latchen,NOT reset,'0'); clklatch_D(4) <= ((clklatch(4) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND cpudata(4) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND cpudata(4) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); clklatchx(0)/clklatchx(0)_D2 <= (NOT useslowclk AND clklatch(0)); clklatchx(1)/clklatchx(1)_D2 <= (NOT useslowclk AND clklatch(1)); clklatchx(2)/clklatchx(2)_D2 <= (NOT useslowclk AND NOT clklatch(2)); clklatchx(3)/clklatchx(3)_D2 <= (NOT useslowclk AND clklatch(3)); clklatchx(4)/clklatchx(4)_D2 <= (NOT useslowclk AND clklatch(4)); cpuclk <= NOT latchen; cpuwnr <= NOT cpurnw; FTCPE_fastclkby2: FTCPE port map (fastclkby2,'1',NOT fastclkin,NOT reset,'0'); FDCPE_fastmode: FDCPE port map (fastmode,fastmode_D,latchen,'0',NOT reset); fastmode_D <= ((fastmode AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(7) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); FDCPE_fastvread: FDCPE port map (fastvread,fastvread_D,latchen,NOT reset,'0'); fastvread_D <= ((fastvread AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(2) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); FDCPE_hidebogus: FDCPE port map (hidebogus,hidebogus_D,latchen,NOT reset,'0'); hidebogus_D <= ((hidebogus AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(3) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); isorig/isorig_D2 <= ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(3) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12) AND cpuaddr_ismyio) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(2) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12)) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT bootrom AND slow64k) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT fastvread AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12))); latchen <= (NOT masterclk AND NOT slowdetected AND NOT slowaccess); FDCPE_masterclk: FDCPE port map (masterclk,BUF_masterclk,NOT fastclkin,NOT masterclk/masterclk_RSTF,'0'); masterclk/masterclk_RSTF <= (reset AND clkenable); nramcs(0) <= NOT (((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT bootrom AND cpurnw AND NOT isorig/isorig_D2 AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND wprotect(1) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT wprotect(0) AND NOT wprotect(1) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(13) AND wprotect(0) AND wprotect(1) AND $OpTx$FX_DC$91) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(18) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(17) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(16) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(15) AND $OpTx$FX_DC$91))); nramcs(1) <= NOT ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND $OpTx$FX_DC$91)); nromcs <= NOT (((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpurnw AND slowaccess AND phi0 AND $OpTx$FX_DC$91) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND slowaccess AND prgrom AND phi0 AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND bootrom AND cpurnw AND slowaccess AND phi0 AND NOT isorig/isorig_D2 AND $OpTx$FX_DC$91))); nromwe <= NOT ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpurnw AND $OpTx$FX_DC$91)); FDCPE_nslowbusclr: FDCPE port map (nslowbusclr,'0',nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,NOT reset,nslowbusclr_PRE); nslowbusclr_PRE <= (slowdetected AND isorig/isorig_D2); nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF <= ((fastmode AND NOT MyClock/phi0D7) OR (NOT fastmode AND NOT MyClock/phi0DD)); FDCPE_nslowdataen: FDCPE port map (nslowdataen,nslowdataen_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,'0',nslowdataen_PRE); nslowdataen_D <= ((NOT reset AND NOT nslowdataen) OR (reset AND slowdetected AND isorig/isorig_D2)); nslowdataen_PRE <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); FDCPE_nslowdataenout: FDCPE port map (nslowdataenout,nslowdataen,fastclkin,'0',NOT reset); phi1 <= NOT phi0; phi2 <= phi0; FDCPE_prgrom: FDCPE port map (prgrom,prgrom_D,latchen,NOT reset,'0'); prgrom_D <= ((prgrom AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(7) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); FDCPE_rnw: FDCPE port map (rnw,rnw_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,NOT reset,'0'); rnw_D <= (NOT cpurnw AND slowdetected AND isorig/isorig_D2); FDCPE_slow64k: FDCPE port map (slow64k,slow64k_D,latchen,'0',NOT reset); slow64k_D <= ((slow64k AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(5) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); FDCPE_slowaccess: FDCPE port map (slowaccess,slowdetected,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,slowaccess/slowaccess_RSTF,'0'); slowaccess/slowaccess_RSTF <= ((NOT reset) OR (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3)); FDCPE_slowaddrlatch: FDCPE port map (slowaddrlatch,slowaddrlatch_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,slowaddrlatch_CLR,NOT reset); slowaddrlatch_D <= (slowdetected AND isorig/isorig_D2); slowaddrlatch_CLR <= (reset AND slowaccess/slowaccess_RSTF); FDCPE_slowdetected: FDCPE port map (slowdetected,slowdetected_D,NOT latchen,NOT slowdetected/slowdetected_RSTF,'0'); slowdetected_D <= ((NOT useslowclk AND hidebogus AND NOT cpuvpa AND NOT cpuvda) OR (NOT cpuaddrin_64k(20) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(23) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(22) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(21) AND NOT useslowclk AND NOT isorig/isorig_D2)); slowdetected/slowdetected_RSTF <= (reset AND NOT MyClockSync/slowdone); FDCPE_useslowclk: FDCPE port map (useslowclk,useslowclk_D,latchen,'0',NOT reset); useslowclk_D <= ((useslowclk AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(4) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); FDCPE_wprotect0: FDCPE port map (wprotect(0),wprotect_D(0),latchen,NOT reset,'0'); wprotect_D(0) <= ((wprotect(0) AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(0) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); FDCPE_wprotect1: FDCPE port map (wprotect(1),wprotect_D(1),latchen,NOT reset,'0'); wprotect_D(1) <= ((wprotect(1) AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(1) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-15-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-15-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 cpuaddrin_2k<12> 43 nramcs<1> 2 cpuaddrin_2k<13> 44 TIE 3 cpuaddrin_2k<14> 45 TIE 4 cpuaddrin_2k<15> 46 TIE 5 cpuaddrin_2k<11> 47 TIE 6 cpuclk 48 TIE 7 nslowdataenout 49 GND 8 GND 50 nromwe 9 phi0 51 TIE 10 fastclkin 52 latchen 11 cpuvpa 53 nromcs 12 phi2 54 cpudata<1> 13 cpuvda 55 cpudata<0> 14 TIE 56 cpudata<3> 15 TIE 57 cpudata<2> 16 GND 58 cpudata<4> 17 cpurnw 59 TDO 18 reset 60 GND 19 bootromin 61 cpudata<6> 20 slowaddrlatch 62 cpudata<7> 21 TIE 63 cpudata<5> 22 VCC 64 VCC 23 phi1 65 TIE 24 TIE 66 cpuaddrin_64k<23> 25 cpuaddr_ismyio 67 cpuaddrin_64k<22> 26 TIE 68 cpuaddrin_64k<21> 27 GND 69 cpuaddrin_64k<20> 28 TDI 70 cpuaddrin_64k<19> 29 TMS 71 cpuaddrin_64k<16> 30 TCK 72 cpuaddrin_64k<17> 31 TIE 73 VCC 32 nslowbusclr 74 TIE 33 rnw 75 cpuaddrin_64k<18> 34 TIE 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 TIE 79 cpuwnr 38 VCC 80 TIE 39 rdy 81 cpuaddrin_16<1> 40 TIE 82 cpuaddrin_16<0> 41 nramcs<0> 83 cpuaddrin_16<3> 42 GND 84 cpuaddrin_16<2> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-15-PC84 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : OFF Pin Feedback : OFF Input Limit : 36 Pterm Limit : 90