********** Mapped Logic ********** |
$OpTx$FX_DC$91 <= ((reset AND cpuvpa AND NOT latchen)
OR (reset AND cpuvda AND NOT latchen)); |
$OpTx$FX_DC$97 <= (NOT clklatchx(1)/clklatchx(1)_D2 AND
NOT clklatchx(0)/clklatchx(0)_D2 AND clklatchx(2)/clklatchx(2)_D2 AND NOT BUF_masterclk); |
$OpTx$FX_DC$98 <= (NOT clklatchx(1)/clklatchx(1)_D2 AND
NOT clklatchx(0)/clklatchx(0)_D2 AND clklatchx(2)/clklatchx(2)_D2 AND NOT BUF_masterclk AND NOT clklatchx(3)/clklatchx(3)_D2); |
BUF_masterclk <= masterclk
XOR BUF_masterclk <= (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3)); |
FDCPE_MyClock/phi0D1: FDCPE port map (MyClock/phi0D1,phi0,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D2: FDCPE port map (MyClock/phi0D2,MyClock/phi0D1,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D3: FDCPE port map (MyClock/phi0D3,MyClock/phi0D2,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D4: FDCPE port map (MyClock/phi0D4,MyClock/phi0D3,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D5: FDCPE port map (MyClock/phi0D5,MyClock/phi0D4,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D6: FDCPE port map (MyClock/phi0D6,MyClock/phi0D5,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D7: FDCPE port map (MyClock/phi0D7,MyClock/phi0D6,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D8: FDCPE port map (MyClock/phi0D8,MyClock/phi0D7,NOT fastclkin,'0','0'); |
FDCPE_MyClock/phi0D9: FDCPE port map (MyClock/phi0D9,MyClock/phi0D8,fastclkby2,'0','0'); |
FDCPE_MyClock/phi0DA: FDCPE port map (MyClock/phi0DA,MyClock/phi0D9,fastclkby2,'0','0'); |
FDCPE_MyClock/phi0DB: FDCPE port map (MyClock/phi0DB,MyClock/phi0DA,fastclkby2,'0','0'); |
FDCPE_MyClock/phi0DC: FDCPE port map (MyClock/phi0DC,MyClock/phi0DB,fastclkby2,'0','0'); |
FDCPE_MyClock/phi0DD: FDCPE port map (MyClock/phi0DD,MyClock/phi0DC,fastclkby2,'0','0'); |
FDCPE_MyClockSync/slowdone: FDCPE port map (MyClockSync/slowdone,MyClockSync/slowdone_D,NOT phi0,MyClockSync/slowdone_CLR,'0');
MyClockSync/slowdone_D <= ((slowaccess AND rdy) OR (MyClockSync/slowdone AND NOT rdy)); MyClockSync/slowdone_CLR <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); |
MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2); |
MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2 <= (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_16(0) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio); |
FDCPE_Mytiming/clkcounter0: FDCPE port map (Mytiming/clkcounter(0),Mytiming/clkcounter_D(0),NOT fastclkin,Mytiming/clkcounter_CLR(0),Mytiming/clkcounter_PRE(0));
Mytiming/clkcounter_D(0) <= ((NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT clklatchx(1)/clklatchx(1)_D2 AND clklatchx(0)/clklatchx(0)_D2) OR (NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND masterclk AND clklatchx(1)/clklatchx(1)_D2 AND masterclk/masterclk_RSTF AND NOT clklatchx(0)/clklatchx(0)_D2) OR (Mytiming/clkcounter(0) AND masterclk/masterclk_RSTF) OR (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT masterclk AND NOT clklatchx(1)/clklatchx(1)_D2)); Mytiming/clkcounter_CLR(0) <= (NOT clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF); Mytiming/clkcounter_PRE(0) <= (clklatchx(1)/clklatchx(1)_D2 AND NOT masterclk/masterclk_RSTF); |
FDCPE_Mytiming/clkcounter1: FDCPE port map (Mytiming/clkcounter(1),Mytiming/clkcounter_D(1),NOT fastclkin,Mytiming/clkcounter_CLR(1),Mytiming/clkcounter_PRE(1));
Mytiming/clkcounter_D(1) <= ((Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(0) AND Mytiming/clkcounter(1) AND masterclk/masterclk_RSTF) OR (NOT masterclk/masterclk_RSTF AND clklatchx(2)/clklatchx(2)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND clklatchx(2)/clklatchx(2)_D2 AND NOT $OpTx$FX_DC$97) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT clklatchx(1)/clklatchx(1)_D2 AND masterclk/masterclk_RSTF AND NOT clklatchx(0)/clklatchx(0)_D2 AND NOT $OpTx$FX_DC$97 AND NOT BUF_masterclk)); Mytiming/clkcounter_CLR(1) <= (NOT masterclk/masterclk_RSTF AND clklatchx(2)/clklatchx(2)_D2); Mytiming/clkcounter_PRE(1) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(2)/clklatchx(2)_D2); |
FDCPE_Mytiming/clkcounter2: FDCPE port map (Mytiming/clkcounter(2),Mytiming/clkcounter_D(2),NOT fastclkin,Mytiming/clkcounter_CLR(2),Mytiming/clkcounter_PRE(2));
Mytiming/clkcounter_D(2) <= ((Mytiming/clkcounter(0) AND Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF) OR (Mytiming/clkcounter(1) AND Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND Mytiming/clkcounter(3) AND masterclk/masterclk_RSTF) OR (NOT masterclk/masterclk_RSTF AND clklatchx(3)/clklatchx(3)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND NOT $OpTx$FX_DC$97 AND clklatchx(3)/clklatchx(3)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF AND $OpTx$FX_DC$97 AND NOT clklatchx(3)/clklatchx(3)_D2)); Mytiming/clkcounter_CLR(2) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(3)/clklatchx(3)_D2); Mytiming/clkcounter_PRE(2) <= (NOT masterclk/masterclk_RSTF AND clklatchx(3)/clklatchx(3)_D2); |
FTCPE_Mytiming/clkcounter3: FTCPE port map (Mytiming/clkcounter(3),Mytiming/clkcounter_T(3),NOT fastclkin,Mytiming/clkcounter_CLR(3),Mytiming/clkcounter_PRE(3));
Mytiming/clkcounter_T(3) <= ((Mytiming/clkcounter(3) AND NOT masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND Mytiming/clkcounter(3) AND masterclk/masterclk_RSTF) OR (NOT Mytiming/clkcounter(3) AND NOT masterclk/masterclk_RSTF AND clklatchx(4)/clklatchx(4)_D2) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND NOT Mytiming/clkcounter(3) AND clklatchx(4)/clklatchx(4)_D2 AND NOT $OpTx$FX_DC$98) OR (NOT Mytiming/clkcounter(0) AND NOT Mytiming/clkcounter(1) AND NOT Mytiming/clkcounter(2) AND masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2 AND $OpTx$FX_DC$98)); Mytiming/clkcounter_CLR(3) <= (NOT masterclk/masterclk_RSTF AND NOT clklatchx(4)/clklatchx(4)_D2); Mytiming/clkcounter_PRE(3) <= (NOT masterclk/masterclk_RSTF AND clklatchx(4)/clklatchx(4)_D2); |
FDCPE_bootrom: FDCPE port map (bootrom,bootrom_D,latchen,bootrom_CLR,bootrom_PRE);
bootrom_D <= ((bootrom AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(6) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); bootrom_CLR <= (NOT reset AND NOT bootromin); bootrom_PRE <= (NOT reset AND bootromin); |
FDCPE_clkenable: FDCPE port map (clkenable,'1',clkenable_C,clkenable_CLR,NOT reset);
clkenable_C <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); clkenable_CLR <= (reset AND slowdetected); |
FDCPE_clklatch0: FDCPE port map (clklatch(0),clklatch_D(0),latchen,'0',NOT reset);
clklatch_D(0) <= ((NOT clklatch(0) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND NOT cpudata(0) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND NOT cpudata(0) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
FDCPE_clklatch1: FDCPE port map (clklatch(1),clklatch_D(1),latchen,'0',NOT reset);
clklatch_D(1) <= ((NOT clklatch(1) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND NOT cpudata(1) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND NOT cpudata(1) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
FDCPE_clklatch2: FDCPE port map (clklatch(2),clklatch_D(2),latchen,'0',NOT reset);
clklatch_D(2) <= ((clklatch(2) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
FDCPE_clklatch3: FDCPE port map (clklatch(3),clklatch_D(3),latchen,'0',NOT reset);
clklatch_D(3) <= ((clklatch(3) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
FDCPE_clklatch4: FDCPE port map (clklatch(4),clklatch_D(4),latchen,NOT reset,'0');
clklatch_D(4) <= ((clklatch(4) AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(3) AND cpudata(4) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(2) AND cpudata(4) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
clklatchx(0)/clklatchx(0)_D2 <= (NOT useslowclk AND clklatch(0)); |
clklatchx(1)/clklatchx(1)_D2 <= (NOT useslowclk AND clklatch(1)); |
clklatchx(2)/clklatchx(2)_D2 <= (NOT useslowclk AND NOT clklatch(2)); |
clklatchx(3)/clklatchx(3)_D2 <= (NOT useslowclk AND clklatch(3)); |
clklatchx(4)/clklatchx(4)_D2 <= (NOT useslowclk AND clklatch(4)); |
cpuclk <= NOT latchen; |
cpuwnr <= NOT cpurnw; |
FTCPE_fastclkby2: FTCPE port map (fastclkby2,'1',NOT fastclkin,NOT reset,'0'); |
FDCPE_fastmode: FDCPE port map (fastmode,fastmode_D,latchen,'0',NOT reset);
fastmode_D <= ((fastmode AND NOT MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2) OR (cpudata(7) AND MyControl/clklatch_or0000/MyControl/clklatch_or0000_D2)); |
FDCPE_fastvread: FDCPE port map (fastvread,fastvread_D,latchen,NOT reset,'0');
fastvread_D <= ((fastvread AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(2) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
FDCPE_hidebogus: FDCPE port map (hidebogus,hidebogus_D,latchen,NOT reset,'0');
hidebogus_D <= ((hidebogus AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(3) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
isorig/isorig_D2 <= ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(3) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12) AND cpuaddr_ismyio) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(2) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12)) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT bootrom AND slow64k) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT fastvread AND NOT cpuaddrin_2k(12)) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_16(1) AND cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_2k(12))); |
latchen <= (NOT masterclk AND NOT slowdetected AND NOT slowaccess); |
FDCPE_masterclk: FDCPE port map (masterclk,BUF_masterclk,NOT fastclkin,NOT masterclk/masterclk_RSTF,'0'); |
masterclk/masterclk_RSTF <= (reset AND clkenable); |
nramcs(0) <= NOT (((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT bootrom AND cpurnw AND NOT isorig/isorig_D2 AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(14) AND wprotect(1) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT wprotect(0) AND NOT wprotect(1) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(13) AND wprotect(0) AND wprotect(1) AND $OpTx$FX_DC$91) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(18) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(17) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND cpuaddrin_64k(16) AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpurnw AND NOT cpuaddrin_2k(15) AND $OpTx$FX_DC$91))); |
nramcs(1) <= NOT ((NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND
NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND $OpTx$FX_DC$91)); |
nromcs <= NOT (((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpurnw AND slowaccess AND phi0 AND $OpTx$FX_DC$91) OR (cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND slowaccess AND prgrom AND phi0 AND $OpTx$FX_DC$91) OR (NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND bootrom AND cpurnw AND slowaccess AND phi0 AND NOT isorig/isorig_D2 AND $OpTx$FX_DC$91))); |
nromwe <= NOT ((cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND
cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpurnw AND $OpTx$FX_DC$91)); |
FDCPE_nslowbusclr: FDCPE port map (nslowbusclr,'0',nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,NOT reset,nslowbusclr_PRE);
nslowbusclr_PRE <= (slowdetected AND isorig/isorig_D2); |
nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF <= ((fastmode AND NOT MyClock/phi0D7)
OR (NOT fastmode AND NOT MyClock/phi0DD)); |
FDCPE_nslowdataen: FDCPE port map (nslowdataen,nslowdataen_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,'0',nslowdataen_PRE);
nslowdataen_D <= ((NOT reset AND NOT nslowdataen) OR (reset AND slowdetected AND isorig/isorig_D2)); nslowdataen_PRE <= (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3); |
FDCPE_nslowdataenout: FDCPE port map (nslowdataenout,nslowdataen,fastclkin,'0',NOT reset); |
phi1 <= NOT phi0; |
phi2 <= phi0; |
FDCPE_prgrom: FDCPE port map (prgrom,prgrom_D,latchen,NOT reset,'0');
prgrom_D <= ((prgrom AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(7) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
FDCPE_rnw: FDCPE port map (rnw,rnw_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,NOT reset,'0');
rnw_D <= (NOT cpurnw AND slowdetected AND isorig/isorig_D2); |
FDCPE_slow64k: FDCPE port map (slow64k,slow64k_D,latchen,'0',NOT reset);
slow64k_D <= ((slow64k AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(5) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
FDCPE_slowaccess: FDCPE port map (slowaccess,slowdetected,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,slowaccess/slowaccess_RSTF,'0'); |
slowaccess/slowaccess_RSTF <= ((NOT reset)
OR (NOT slowdetected AND NOT MyClock/phi0D2 AND MyClock/phi0D3)); |
FDCPE_slowaddrlatch: FDCPE port map (slowaddrlatch,slowaddrlatch_D,nslowbusclr_OBUF/nslowbusclr_OBUF_CLKF,slowaddrlatch_CLR,NOT reset);
slowaddrlatch_D <= (slowdetected AND isorig/isorig_D2); slowaddrlatch_CLR <= (reset AND slowaccess/slowaccess_RSTF); |
FDCPE_slowdetected: FDCPE port map (slowdetected,slowdetected_D,NOT latchen,NOT slowdetected/slowdetected_RSTF,'0');
slowdetected_D <= ((NOT useslowclk AND hidebogus AND NOT cpuvpa AND NOT cpuvda) OR (NOT cpuaddrin_64k(20) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(23) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(22) AND NOT useslowclk AND NOT isorig/isorig_D2) OR (NOT cpuaddrin_64k(21) AND NOT useslowclk AND NOT isorig/isorig_D2)); |
slowdetected/slowdetected_RSTF <= (reset AND NOT MyClockSync/slowdone); |
FDCPE_useslowclk: FDCPE port map (useslowclk,useslowclk_D,latchen,'0',NOT reset);
useslowclk_D <= ((useslowclk AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(4) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
FDCPE_wprotect0: FDCPE port map (wprotect(0),wprotect_D(0),latchen,NOT reset,'0');
wprotect_D(0) <= ((wprotect(0) AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(0) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
FDCPE_wprotect1: FDCPE port map (wprotect(1),wprotect_D(1),latchen,NOT reset,'0');
wprotect_D(1) <= ((wprotect(1) AND NOT MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2) OR (cpudata(1) AND MyControl/bootrom_or0000/MyControl/bootrom_or0000_D2)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |