Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
cpuclk 1 3 FB1 MC9 STD FAST 6 I/O O  
nslowdataen 4 21 FB1 MC11 STD FAST 7 I/O O  
Mytiming/clkcounter<3>/Mytiming/clkcounter<3>_RSTF 2 3 FB1 MC13 STD     (b) (b)  
Mytiming/clkcounter<2>/Mytiming/clkcounter<2>_RSTF 2 3 FB1 MC14 STD   10 I/O/GCK2 GCK  
slowonly 4 25 FB1 MC15 STD   11 I/O I RESET
bogusok 4 25 FB1 MC16 STD   12 I/O/GCK3 GCK/I RESET
clklatch<3> 5 26 FB1 MC17 STD   13 I/O I RESET
clklatch<2> 5 26 FB1 MC18 STD     (b) (b) RESET
MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT 1 2 FB2 MC12 STD   80 I/O (b)  
diag_OBUF/diag_OBUF_RSTF 2 3 FB2 MC13 STD     (b) (b)  
slowaccess 3 3 FB2 MC14 STD   81 I/O I RESET
MyClockSync/slowdone 3 4 FB2 MC15 STD   82 I/O I RESET
wprotect<1> 4 25 FB2 MC16 STD   83 I/O I RESET
wprotect<0> 4 25 FB2 MC17 STD   84 I/O I RESET
slow64k 4 25 FB2 MC18 STD     (b) (b) RESET
norom 1 3 FB3 MC3 STD FAST 15 I/O O  
nslowbusen 1 3 FB3 MC9 STD FAST 20 I/O O  
Mytiming/clkcounter<1>/Mytiming/clkcounter<1>_RSTF 2 3 FB3 MC15 STD   25 I/O I  
clklatch<1> 5 26 FB3 MC16 STD   26 I/O (b) RESET
clklatch<0> 5 26 FB3 MC17 STD   31 I/O (b) RESET
bootrom 5 26 FB3 MC18 STD     (b) (b) RESET
fastclkby2 0 0 FB4 MC9 STD   65 I/O (b) RESET
fastclkbydiv 2 5 FB4 MC10 STD     (b) (b) RESET
Mytiming/clkcounter<0> 5 7 FB4 MC11 STD   66 I/O I RESET
Mytiming/clkcounter<3> 6 7 FB4 MC12 STD   67 I/O I RESET
Mytiming/clkcounter<1> 6 7 FB4 MC13 STD     (b) (b) RESET
Mytiming/clkcounter<2> 7 7 FB4 MC15 STD   69 I/O I RESET
MyClockSync/slowdetected 17 21 FB4 MC18 STD     (b) (b) RESET
MyClock/phi0D5 2 2 FB5 MC1 STD     (b) (b) RESET
nslowbusclr 1 2 FB5 MC2 STD FAST 32 I/O O  
rnw 1 4 FB5 MC3 STD FAST 33 I/O O  
fastclkbydiv/fastclkbydiv_RSTF__$INT 1 2 FB5 MC7 STD     (b) (b)  
cpuclk_OBUF/cpuclk_OBUF_D2__$INT 1 3 FB5 MC8 STD   36 I/O (b)  
slowaccess/slowaccess_RSTF 2 4 FB5 MC9 STD   37 I/O (b)  
extclkdel 2 2 FB5 MC10 STD     (b) (b) RESET
MyClock/phi0D4 2 2 FB5 MC11 STD   39 I/O I RESET
nramcs<0> 16 24 FB5 MC14 STD FAST 41 I/O O  
nramcs<1> 6 11 FB5 MC15 STD FAST 43 I/O O  
validaddrdel 3 4 FB5 MC16 STD     (b) (b) RESET
clocked_rnw 3 3 FB5 MC17 STD   44 I/O (b) RESET
isorigdel 6 17 FB5 MC18 STD     (b) (b) RESET
nromwe 6 12 FB6 MC8 STD FAST 50 I/O O  
diag 2 2 FB6 MC9 STD FAST 51 I/O I/O RESET
latchen 1 3 FB6 MC11 STD FAST 52 I/O O  
nromcs 14 21 FB6 MC12 STD FAST 53 I/O O  
Mytiming/clkcounter<0>/Mytiming/clkcounter<0>_RSTF 2 3 FB6 MC13 STD     (b) (b)  
MyClock/phi0D3 2 2 FB6 MC15 STD   55 I/O I RESET
MyClock/phi0D2 2 2 FB6 MC16 STD     (b) (b) RESET
MyClock/phi0D1 2 2 FB6 MC17 STD   56 I/O I RESET
prgrom 4 25 FB6 MC18 STD     (b) (b) RESET