cpldfit: version L.33 Xilinx Inc. Fitter Report Design Name: PET816 Date: 4-20-2010, 7:36PM Device Used: XC95108-15-PC84 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 50 /108 ( 46%) 191 /540 ( 35%) 201/216 ( 93%) 30 /108 ( 28%) 46 /69 ( 67%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 8/18 32/36 32 27/90 2/12 FB2 7/18 34/36 34 21/90 0/12 FB3 6/18 32/36 32 19/90 2/12 FB4 7/18 35/36 35 43/90 0/11 FB5 13/18 33/36 33 46/90 4/11 FB6 9/18 35/36 35 35/90 4/11 ----- ----- ----- ----- 50/108 201/216 191/540 12/69 * - Resource is exhausted ** Global Control Resources ** The complement of 'fastclkin' mapped onto global clock net GCK2. The complement of 'phi2' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 32 32 | I/O : 44 63 Output : 11 11 | GCK/IO : 2 3 Bidirectional : 1 1 | GTS/IO : 0 2 GCK : 2 2 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 46 46 ** Power Data ** There are 50 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'fastclkin' based upon the LOC constraint 'P10'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'phi2' based upon the LOC constraint 'P12'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'phi0' based upon the LOC constraint 'P9'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1007 - Removing unused input(s) 'cpuvp'. The input(s) are unused after optimization. Please verify functionality via simulation. WARNING:Cpld:1007 - Removing unused input(s) 'phi0'. The input(s) are unused after optimization. Please verify functionality via simulation. ************************* Summary of Mapped Logic ************************ ** 12 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State cpuclk 1 3 FB1_9 6 I/O O STD FAST nslowdataen 4 21 FB1_11 7 I/O O STD FAST norom 1 3 FB3_3 15 I/O O STD FAST nslowbusen 1 3 FB3_9 20 I/O O STD FAST nslowbusclr 1 2 FB5_2 32 I/O O STD FAST rnw 1 4 FB5_3 33 I/O O STD FAST nramcs<0> 16 24 FB5_14 41 I/O O STD FAST nramcs<1> 6 11 FB5_15 43 I/O O STD FAST nromwe 6 12 FB6_8 50 I/O O STD FAST diag 2 2 FB6_9 51 I/O I/O STD FAST RESET latchen 1 3 FB6_11 52 I/O O STD FAST nromcs 14 21 FB6_12 53 I/O O STD FAST ** 38 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State Mytiming/clkcounter<3>/Mytiming/clkcounter<3>_RSTF 2 3 FB1_13 STD Mytiming/clkcounter<2>/Mytiming/clkcounter<2>_RSTF 2 3 FB1_14 STD slowonly 4 25 FB1_15 STD RESET bogusok 4 25 FB1_16 STD RESET clklatch<3> 5 26 FB1_17 STD RESET clklatch<2> 5 26 FB1_18 STD RESET MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT 1 2 FB2_12 STD diag_OBUF/diag_OBUF_RSTF 2 3 FB2_13 STD slowaccess 3 3 FB2_14 STD RESET MyClockSync/slowdone 3 4 FB2_15 STD RESET wprotect<1> 4 25 FB2_16 STD RESET wprotect<0> 4 25 FB2_17 STD RESET slow64k 4 25 FB2_18 STD RESET Mytiming/clkcounter<1>/Mytiming/clkcounter<1>_RSTF 2 3 FB3_15 STD clklatch<1> 5 26 FB3_16 STD RESET clklatch<0> 5 26 FB3_17 STD RESET bootrom 5 26 FB3_18 STD RESET fastclkby2 0 0 FB4_9 STD RESET fastclkbydiv 2 5 FB4_10 STD RESET Mytiming/clkcounter<0> 5 7 FB4_11 STD RESET Mytiming/clkcounter<3> 6 7 FB4_12 STD RESET Mytiming/clkcounter<1> 6 7 FB4_13 STD RESET Mytiming/clkcounter<2> 7 7 FB4_15 STD RESET MyClockSync/slowdetected 17 21 FB4_18 STD RESET MyClock/phi0D5 2 2 FB5_1 STD RESET fastclkbydiv/fastclkbydiv_RSTF__$INT 1 2 FB5_7 STD cpuclk_OBUF/cpuclk_OBUF_D2__$INT 1 3 FB5_8 STD slowaccess/slowaccess_RSTF 2 4 FB5_9 STD extclkdel 2 2 FB5_10 STD RESET MyClock/phi0D4 2 2 FB5_11 STD RESET validaddrdel 3 4 FB5_16 STD RESET clocked_rnw 3 3 FB5_17 STD RESET isorigdel 6 17 FB5_18 STD RESET Mytiming/clkcounter<0>/Mytiming/clkcounter<0>_RSTF 2 3 FB6_13 STD MyClock/phi0D3 2 2 FB6_15 STD RESET MyClock/phi0D2 2 2 FB6_16 STD RESET MyClock/phi0D1 2 2 FB6_17 STD RESET prgrom 4 25 FB6_18 STD RESET ** 34 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use cpuaddrin_2k<12> FB1_2 1 I/O I cpuaddrin_2k<13> FB1_3 2 I/O I cpuaddrin_2k<14> FB1_5 3 I/O I cpuaddrin_2k<15> FB1_6 4 I/O I cpuaddrin_2k<11> FB1_8 5 I/O I fastclkin FB1_14 10 GCK/I/O GCK cpuvpa FB1_15 11 I/O I phi2 FB1_16 12 GCK/I/O GCK/I cpuvda FB1_17 13 I/O I cpuaddrin_64k<16> FB2_2 71 I/O I cpuaddrin_64k<17> FB2_3 72 I/O I cpuaddrin_64k<18> FB2_6 75 I/O I cpuaddrin_16<1> FB2_14 81 I/O I cpuaddrin_16<0> FB2_15 82 I/O I cpuaddrin_16<3> FB2_16 83 I/O I cpuaddrin_16<2> FB2_17 84 I/O I cpurnw FB3_5 17 I/O I reset FB3_6 18 I/O I bootromin FB3_8 19 I/O I cpuaddr_ismyio FB3_15 25 I/O I cpudata<2> FB4_2 57 I/O I cpudata<4> FB4_3 58 I/O I cpudata<6> FB4_5 61 I/O I cpudata<7> FB4_6 62 I/O I cpudata<5> FB4_8 63 I/O I cpuaddrin_64k<23> FB4_11 66 I/O I cpuaddrin_64k<22> FB4_12 67 I/O I cpuaddrin_64k<21> FB4_14 68 I/O I cpuaddrin_64k<20> FB4_15 69 I/O I cpuaddrin_64k<19> FB4_17 70 I/O I rdy FB5_11 39 I/O I cpudata<1> FB6_14 54 I/O I cpudata<0> FB6_15 55 I/O I cpudata<3> FB6_17 56 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 1 I/O I (unused) 0 0 0 5 FB1_3 2 I/O I (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 3 I/O I (unused) 0 0 0 5 FB1_6 4 I/O I (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 5 I/O I cpuclk 1 0 0 4 FB1_9 6 I/O O (unused) 0 0 0 5 FB1_10 (b) nslowdataen 4 0 0 1 FB1_11 7 I/O O (unused) 0 0 0 5 FB1_12 9 GCK/I/O Mytiming/clkcounter<3>/Mytiming/clkcounter<3>_RSTF 2 0 0 3 FB1_13 (b) (b) Mytiming/clkcounter<2>/Mytiming/clkcounter<2>_RSTF 2 0 0 3 FB1_14 10 GCK/I/O GCK slowonly 4 0 0 1 FB1_15 11 I/O I bogusok 4 0 0 1 FB1_16 12 GCK/I/O GCK/I clklatch<3> 5 0 0 0 FB1_17 13 I/O I clklatch<2> 5 0 0 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: bogusok.LFBK 12: cpuaddrin_2k<14> 23: cpudata<1> 2: clklatch<2>.LFBK 13: cpuaddrin_2k<15> 24: cpudata<4> 3: clklatch<3>.LFBK 14: cpuaddrin_64k<16> 25: cpurnw 4: cpuaddr_ismyio 15: cpuaddrin_64k<17> 26: diag.PIN 5: cpuaddrin_16<0> 16: cpuaddrin_64k<18> 27: fastclkbydiv 6: cpuaddrin_16<1> 17: cpuaddrin_64k<19> 28: isorigdel 7: cpuaddrin_16<2> 18: cpuaddrin_64k<20> 29: reset 8: cpuaddrin_16<3> 19: cpuaddrin_64k<21> 30: slowaccess 9: cpuaddrin_2k<11> 20: cpuaddrin_64k<22> 31: slowonly.LFBK 10: cpuaddrin_2k<12> 21: cpuaddrin_64k<23> 32: validaddrdel 11: cpuaddrin_2k<13> 22: cpudata<0> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs cpuclk .........................XX..X.......... 3 3 nslowdataen ...XXXXXXXXXXXXXXXXXX......X.X.X........ 21 21 Mytiming/clkcounter<3>/Mytiming/clkcounter<3>_RSTF ..X.........................XX.......... 3 3 Mytiming/clkcounter<2>/Mytiming/clkcounter<2>_RSTF .X..........................XX.......... 3 3 slowonly ...XXXXXXXXXXXXXXXXXX..XXXX.XXX......... 25 25 bogusok X..XXXXXXXXXXXXXXXXXX..XXXX.XX.......... 25 25 clklatch<3> ..XXXXXXXXXXXXXXXXXXXXX.XXX.XX.......... 26 26 clklatch<2> .X.XXXXXXXXXXXXXXXXXXXX.XXX.XX.......... 26 26 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 34/2 Number of signals used by logic mapping into function block: 34 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 71 I/O I (unused) 0 0 0 5 FB2_3 72 I/O I (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 74 GSR/I/O (unused) 0 0 0 5 FB2_6 75 I/O I (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 76 GTS/I/O (unused) 0 0 0 5 FB2_9 77 GTS/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 79 I/O MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT 1 0 0 4 FB2_12 80 I/O (b) diag_OBUF/diag_OBUF_RSTF 2 0 0 3 FB2_13 (b) (b) slowaccess 3 0 0 2 FB2_14 81 I/O I MyClockSync/slowdone 3 0 0 2 FB2_15 82 I/O I wprotect<1> 4 0 0 1 FB2_16 83 I/O I wprotect<0> 4 0 0 1 FB2_17 84 I/O I slow64k 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: MyClockSync/slowdetected 13: cpuaddrin_64k<16> 24: cpurnw 2: MyClockSync/slowdone.LFBK 14: cpuaddrin_64k<17> 25: diag.PIN 3: cpuaddr_ismyio 15: cpuaddrin_64k<18> 26: extclkdel 4: cpuaddrin_16<0> 16: cpuaddrin_64k<19> 27: fastclkbydiv 5: cpuaddrin_16<1> 17: cpuaddrin_64k<20> 28: rdy 6: cpuaddrin_16<2> 18: cpuaddrin_64k<21> 29: reset 7: cpuaddrin_16<3> 19: cpuaddrin_64k<22> 30: slow64k.LFBK 8: cpuaddrin_2k<11> 20: cpuaddrin_64k<23> 31: slowaccess.LFBK 9: cpuaddrin_2k<12> 21: cpudata<2> 32: slowaccess/slowaccess_RSTF 10: cpuaddrin_2k<13> 22: cpudata<3> 33: wprotect<0>.LFBK 11: cpuaddrin_2k<14> 23: cpudata<5> 34: wprotect<1>.LFBK 12: cpuaddrin_2k<15> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT .X..........................X........... 2 2 diag_OBUF/diag_OBUF_RSTF .........................X..X.X......... 3 3 slowaccess X........................X.....X........ 3 3 MyClockSync/slowdone .X.........................X..XX........ 4 4 wprotect<1> ..XXXXXXXXXXXXXXXXXX.X.XX.X.X.X..X...... 25 25 wprotect<0> ..XXXXXXXXXXXXXXXXXXX..XX.X.X.X.X....... 25 25 slow64k ..XXXXXXXXXXXXXXXXXX..XXX.X.XXX......... 25 25 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 32/4 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 14 I/O norom 1 0 0 4 FB3_3 15 I/O O (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 17 I/O I (unused) 0 0 0 5 FB3_6 18 I/O I (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 19 I/O I nslowbusen 1 0 0 4 FB3_9 20 I/O O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 21 I/O (unused) 0 0 0 5 FB3_12 23 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 24 I/O Mytiming/clkcounter<1>/Mytiming/clkcounter<1>_RSTF 2 0 0 3 FB3_15 25 I/O I clklatch<1> 5 0 0 0 FB3_16 26 I/O (b) clklatch<0> 5 0 0 0 FB3_17 31 I/O (b) bootrom 5 0 0 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: bootrom.LFBK 12: cpuaddrin_2k<13> 23: cpudata<0> 2: bootromin 13: cpuaddrin_2k<14> 24: cpudata<1> 3: clklatch<0>.LFBK 14: cpuaddrin_2k<15> 25: cpudata<6> 4: clklatch<1>.LFBK 15: cpuaddrin_64k<16> 26: cpurnw 5: cpuaddr_ismyio 16: cpuaddrin_64k<17> 27: diag.PIN 6: cpuaddrin_16<0> 17: cpuaddrin_64k<18> 28: fastclkbydiv 7: cpuaddrin_16<1> 18: cpuaddrin_64k<19> 29: isorigdel 8: cpuaddrin_16<2> 19: cpuaddrin_64k<20> 30: reset 9: cpuaddrin_16<3> 20: cpuaddrin_64k<21> 31: slowaccess 10: cpuaddrin_2k<11> 21: cpuaddrin_64k<22> 32: validaddrdel 11: cpuaddrin_2k<12> 22: cpuaddrin_64k<23> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs norom ............................X.XX........ 3 3 nslowbusen ............................X.XX........ 3 3 Mytiming/clkcounter<1>/Mytiming/clkcounter<1>_RSTF ...X.........................XX......... 3 3 clklatch<1> ...XXXXXXXXXXXXXXXXXXXXX.XXX.XX......... 26 26 clklatch<0> ..X.XXXXXXXXXXXXXXXXXXXX.XXX.XX......... 26 26 bootrom XX..XXXXXXXXXXXXXXXXXX..XXXX.XX......... 26 26 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 35/1 Number of signals used by logic mapping into function block: 35 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB4_1 (b) (b) (unused) 0 0 /\2 3 FB4_2 57 I/O I (unused) 0 0 0 5 FB4_3 58 I/O I (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 61 I/O I (unused) 0 0 0 5 FB4_6 62 I/O I (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 63 I/O I fastclkby2 0 0 0 5 FB4_9 65 I/O (b) fastclkbydiv 2 0 0 3 FB4_10 (b) (b) Mytiming/clkcounter<0> 5 0 0 0 FB4_11 66 I/O I Mytiming/clkcounter<3> 6 1<- 0 0 FB4_12 67 I/O I Mytiming/clkcounter<1> 6 2<- /\1 0 FB4_13 (b) (b) (unused) 0 0 /\2 3 FB4_14 68 I/O I Mytiming/clkcounter<2> 7 2<- 0 0 FB4_15 69 I/O I (unused) 0 0 /\2 3 FB4_16 (b) (b) (unused) 0 0 \/5 0 FB4_17 70 I/O I MyClockSync/slowdetected 17 12<- 0 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT 13: clklatch<1> 25: cpuaddrin_64k<20> 2: Mytiming/clkcounter<0>.LFBK 14: clklatch<2> 26: cpuaddrin_64k<21> 3: Mytiming/clkcounter<0>/Mytiming/clkcounter<0>_RSTF 15: clklatch<3> 27: cpuaddrin_64k<22> 4: Mytiming/clkcounter<1>.LFBK 16: cpuaddrin_2k<11> 28: cpuaddrin_64k<23> 5: Mytiming/clkcounter<1>/Mytiming/clkcounter<1>_RSTF 17: cpuaddrin_2k<12> 29: cpuclk_OBUF/cpuclk_OBUF_D2__$INT 6: Mytiming/clkcounter<2>.LFBK 18: cpuaddrin_2k<13> 30: cpuvda 7: Mytiming/clkcounter<2>/Mytiming/clkcounter<2>_RSTF 19: cpuaddrin_2k<14> 31: cpuvpa 8: Mytiming/clkcounter<3>.LFBK 20: cpuaddrin_2k<15> 32: fastclkbydiv/fastclkbydiv_RSTF__$INT 9: Mytiming/clkcounter<3>/Mytiming/clkcounter<3>_RSTF 21: cpuaddrin_64k<16> 33: slow64k 10: bogusok 22: cpuaddrin_64k<17> 34: slowaccess 11: bootrom 23: cpuaddrin_64k<18> 35: slowonly 12: clklatch<0> 24: cpuaddrin_64k<19> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs fastclkby2 ........................................ 0 0 fastclkbydiv .X.X.X.X.......................X........ 5 5 Mytiming/clkcounter<0> .XXX.X.X...X.....................X...... 7 7 Mytiming/clkcounter<3> .X.X.X.XX.....X..................X...... 7 7 Mytiming/clkcounter<1> .X.XXX.X....X....................X...... 7 7 Mytiming/clkcounter<2> .X.X.XXX.....X...................X...... 7 7 MyClockSync/slowdetected X........XX....XXXXXXXXXXXXXXXX.X.X..... 21 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 33/3 Number of signals used by logic mapping into function block: 33 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use MyClock/phi0D5 2 0 /\1 2 FB5_1 (b) (b) nslowbusclr 1 0 0 4 FB5_2 32 I/O O rnw 1 0 0 4 FB5_3 33 I/O O (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 34 I/O (unused) 0 0 0 5 FB5_6 35 I/O fastclkbydiv/fastclkbydiv_RSTF__$INT 1 0 0 4 FB5_7 (b) (b) cpuclk_OBUF/cpuclk_OBUF_D2__$INT 1 0 0 4 FB5_8 36 I/O (b) slowaccess/slowaccess_RSTF 2 0 0 3 FB5_9 37 I/O (b) extclkdel 2 0 0 3 FB5_10 (b) (b) MyClock/phi0D4 2 0 0 3 FB5_11 39 I/O I (unused) 0 0 \/5 0 FB5_12 40 I/O (b) (unused) 0 0 \/5 0 FB5_13 (b) (b) nramcs<0> 16 11<- 0 0 FB5_14 41 I/O O nramcs<1> 6 2<- /\1 0 FB5_15 43 I/O O validaddrdel 3 0 /\2 0 FB5_16 (b) (b) clocked_rnw 3 0 0 2 FB5_17 44 I/O (b) isorigdel 6 1<- 0 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: MyClock/phi0D2 12: cpuaddrin_64k<16> 23: cpuvpa 2: MyClock/phi0D3 13: cpuaddrin_64k<17> 24: diag.PIN 3: MyClock/phi0D4.LFBK 14: cpuaddrin_64k<18> 25: fastclkby2 4: MyClock/phi0D5.LFBK 15: cpuaddrin_64k<19> 26: fastclkbydiv 5: bootrom 16: cpuaddrin_64k<20> 27: isorigdel.LFBK 6: clocked_rnw.LFBK 17: cpuaddrin_64k<21> 28: reset 7: cpuaddrin_2k<11> 18: cpuaddrin_64k<22> 29: slow64k 8: cpuaddrin_2k<12> 19: cpuaddrin_64k<23> 30: slowaccess 9: cpuaddrin_2k<13> 20: cpuclk_OBUF/cpuclk_OBUF_D2__$INT.LFBK 31: validaddrdel.LFBK 10: cpuaddrin_2k<14> 21: cpurnw 32: wprotect<0> 11: cpuaddrin_2k<15> 22: cpuvda 33: wprotect<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs MyClock/phi0D5 ..X.....................X............... 2 2 nslowbusclr ..XX.................................... 2 2 rnw .....X....................X..XX......... 4 4 fastclkbydiv/fastclkbydiv_RSTF__$INT ...........................X.X.......... 2 2 cpuclk_OBUF/cpuclk_OBUF_D2__$INT .......................X.X...X.......... 3 3 slowaccess/slowaccess_RSTF XXX..X.................................. 4 4 extclkdel ...X....................X............... 2 2 MyClock/phi0D4 .X......................X............... 2 2 nramcs<0> ....X.XXXXXXXXXXXXX.XXXX.X.XXX.XX....... 24 24 nramcs<1> ..............XXXXX..XXX.X.X.X.......... 11 11 validaddrdel ...................X.XX....X............ 4 4 clocked_rnw ...................XX......X............ 3 3 isorigdel ....X.XXXXXXXXXXXXXX.......XX........... 17 17 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 35/1 Number of signals used by logic mapping into function block: 35 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 45 I/O (unused) 0 0 0 5 FB6_3 46 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 47 I/O (unused) 0 0 0 5 FB6_6 48 I/O (unused) 0 0 \/1 4 FB6_7 (b) (b) nromwe 6 1<- 0 0 FB6_8 50 I/O O diag 2 0 0 3 FB6_9 51 I/O I/O (unused) 0 0 \/1 4 FB6_10 (b) (b) latchen 1 1<- \/5 0 FB6_11 52 I/O O nromcs 14 9<- 0 0 FB6_12 53 I/O O Mytiming/clkcounter<0>/Mytiming/clkcounter<0>_RSTF 2 1<- /\4 0 FB6_13 (b) (b) (unused) 0 0 /\1 4 FB6_14 54 I/O I MyClock/phi0D3 2 0 0 3 FB6_15 55 I/O I MyClock/phi0D2 2 0 0 3 FB6_16 (b) (b) MyClock/phi0D1 2 0 0 3 FB6_17 56 I/O I prgrom 4 0 0 1 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: MyClock/phi0D1.LFBK 13: cpuaddrin_2k<13> 25: cpurnw 2: MyClock/phi0D2.LFBK 14: cpuaddrin_2k<14> 26: cpuvda 3: MyClockSync/slowdetected 15: cpuaddrin_2k<15> 27: cpuvpa 4: bootrom 16: cpuaddrin_64k<16> 28: diag_OBUF.LFBK 5: clklatch<0> 17: cpuaddrin_64k<17> 29: diag_OBUF/diag_OBUF_RSTF 6: cpuaddr_ismyio 18: cpuaddrin_64k<18> 30: fastclkby2 7: cpuaddrin_16<0> 19: cpuaddrin_64k<19> 31: fastclkbydiv 8: cpuaddrin_16<1> 20: cpuaddrin_64k<20> 32: phi2 9: cpuaddrin_16<2> 21: cpuaddrin_64k<21> 33: prgrom.LFBK 10: cpuaddrin_16<3> 22: cpuaddrin_64k<22> 34: reset 11: cpuaddrin_2k<11> 23: cpuaddrin_64k<23> 35: slowaccess 12: cpuaddrin_2k<12> 24: cpudata<7> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs nromwe ..................XXXXX.XXXX..X..XX..... 12 12 diag ..X.........................X........... 2 2 latchen ...........................X..X...X..... 3 3 nromcs ...X......XXXXXXXXXXXXX.XXX....XXXX..... 21 21 Mytiming/clkcounter<0>/Mytiming/clkcounter<0>_RSTF ....X............................XX..... 3 3 MyClock/phi0D3 .X...........................X.......... 2 2 MyClock/phi0D2 X............................X.......... 2 2 MyClock/phi0D1 .............................X.X........ 2 2 prgrom .....XXXXXXXXXXXXXXXXXXXX..X..X.XXX..... 25 25 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_MyClock/phi0D1: FDCPE port map (MyClock/phi0D1,phi2,NOT fastclkby2,'0','0'); FDCPE_MyClock/phi0D2: FDCPE port map (MyClock/phi0D2,MyClock/phi0D1.LFBK,NOT fastclkby2,'0','0'); FDCPE_MyClock/phi0D3: FDCPE port map (MyClock/phi0D3,MyClock/phi0D2.LFBK,NOT fastclkby2,'0','0'); FDCPE_MyClock/phi0D4: FDCPE port map (MyClock/phi0D4,MyClock/phi0D3,NOT fastclkby2,'0','0'); FDCPE_MyClock/phi0D5: FDCPE port map (MyClock/phi0D5,MyClock/phi0D4.LFBK,NOT fastclkby2,'0','0'); FDCPE_MyClockSync/slowdetected: FDCPE port map (MyClockSync/slowdetected,MyClockSync/slowdetected_D,NOT cpuclk_OBUF/cpuclk_OBUF_D2__$INT,NOT MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT,'0'); MyClockSync/slowdetected_D <= ((EXP1_.EXP) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT bootrom AND bogusok AND slow64k) OR (cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND cpuvpa) OR (cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND cpuvda) OR (cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bogusok) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND cpuvpa) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuvpa) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND cpuvda) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND bogusok) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT bootrom AND cpuvpa AND slow64k) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT bootrom AND cpuvda AND slow64k) OR (cpuvpa AND slowonly) OR (cpuvda AND slowonly) OR (bogusok AND slowonly)); MyClockSync/slowdetected/MyClockSync/slowdetected_RSTF__$INT <= (reset AND NOT MyClockSync/slowdone.LFBK); FDCPE_MyClockSync/slowdone: FDCPE port map (MyClockSync/slowdone,MyClockSync/slowdone_D,NOT phi2,slowaccess/slowaccess_RSTF,'0'); MyClockSync/slowdone_D <= ((rdy AND slowaccess.LFBK) OR (NOT rdy AND MyClockSync/slowdone.LFBK)); FDCPE_Mytiming/clkcounter0: FDCPE port map (Mytiming/clkcounter(0),Mytiming/clkcounter_D(0),NOT fastclkin,Mytiming/clkcounter(0)/Mytiming/clkcounter(0)_RSTF,Mytiming/clkcounter_PRE(0)); Mytiming/clkcounter_D(0) <= ((slowaccess AND NOT clklatch(0)) OR (NOT slowaccess AND Mytiming/clkcounter(0).LFBK) OR (NOT clklatch(0) AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND NOT Mytiming/clkcounter(3).LFBK)); Mytiming/clkcounter_PRE(0) <= (slowaccess AND clklatch(0)); Mytiming/clkcounter(0)/Mytiming/clkcounter(0)_RSTF <= ((NOT reset) OR (slowaccess AND NOT clklatch(0))); Mytiming/clkcounter(1)/Mytiming/clkcounter(1)_RSTF <= ((NOT reset) OR (slowaccess AND NOT clklatch(1).LFBK)); FDCPE_Mytiming/clkcounter1: FDCPE port map (Mytiming/clkcounter(1),Mytiming/clkcounter_D(1),NOT fastclkin,Mytiming/clkcounter(1)/Mytiming/clkcounter(1)_RSTF,Mytiming/clkcounter_PRE(1)); Mytiming/clkcounter_D(1) <= ((NOT slowaccess AND Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK) OR (NOT clklatch(1) AND NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND NOT Mytiming/clkcounter(3).LFBK) OR (slowaccess AND NOT clklatch(1)) OR (NOT slowaccess AND NOT Mytiming/clkcounter(0).LFBK AND Mytiming/clkcounter(1).LFBK)); Mytiming/clkcounter_PRE(1) <= (slowaccess AND clklatch(1)); FDCPE_Mytiming/clkcounter2: FDCPE port map (Mytiming/clkcounter(2),Mytiming/clkcounter_D(2),NOT fastclkin,Mytiming/clkcounter(2)/Mytiming/clkcounter(2)_RSTF,Mytiming/clkcounter_PRE(2)); Mytiming/clkcounter_D(2) <= ((NOT slowaccess AND Mytiming/clkcounter(1).LFBK AND Mytiming/clkcounter(2).LFBK) OR (NOT slowaccess AND NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND Mytiming/clkcounter(3).LFBK) OR (slowaccess AND clklatch(2)) OR (NOT slowaccess AND Mytiming/clkcounter(0).LFBK AND Mytiming/clkcounter(2).LFBK) OR (clklatch(2) AND NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK)); Mytiming/clkcounter_PRE(2) <= (slowaccess AND clklatch(2)); Mytiming/clkcounter(2)/Mytiming/clkcounter(2)_RSTF <= ((NOT reset) OR (slowaccess AND NOT clklatch(2).LFBK)); Mytiming/clkcounter(3)/Mytiming/clkcounter(3)_RSTF <= ((NOT reset) OR (slowaccess AND NOT clklatch(3).LFBK)); FTCPE_Mytiming/clkcounter3: FTCPE port map (Mytiming/clkcounter(3),Mytiming/clkcounter_T(3),NOT fastclkin,Mytiming/clkcounter(3)/Mytiming/clkcounter(3)_RSTF,Mytiming/clkcounter_PRE(3)); Mytiming/clkcounter_T(3) <= ((clklatch(3) AND NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND NOT Mytiming/clkcounter(3).LFBK) OR (slowaccess AND clklatch(3) AND NOT Mytiming/clkcounter(3).LFBK) OR (slowaccess AND NOT clklatch(3) AND Mytiming/clkcounter(3).LFBK) OR (NOT slowaccess AND NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND Mytiming/clkcounter(3).LFBK)); Mytiming/clkcounter_PRE(3) <= (slowaccess AND clklatch(3)); FTCPE_bogusok: FTCPE port map (bogusok,bogusok_T,bogusok_C,'0',NOT reset); bogusok_T <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(4) AND NOT bogusok.LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(4) AND bogusok.LFBK)); bogusok_C <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FTCPE_bootrom: FTCPE port map (bootrom,bootrom_T,bootrom_C,bootrom_CLR,bootrom_PRE); bootrom_T <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(6) AND NOT bootrom.LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(6) AND bootrom.LFBK)); bootrom_C <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); bootrom_CLR <= (NOT reset AND NOT bootromin); bootrom_PRE <= (NOT reset AND bootromin); FTCPE_clklatch0: FTCPE port map (clklatch(0),clklatch_T(0),clklatch_C(0),'0',NOT reset); clklatch_T(0) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(1) AND NOT clklatch(0).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(0) AND NOT clklatch(0).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(1) AND cpudata(0) AND clklatch(0).LFBK)); clklatch_C(0) <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FTCPE_clklatch1: FTCPE port map (clklatch(1),clklatch_T(1),clklatch_C(1),NOT reset,'0'); clklatch_T(1) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(1) AND clklatch(1).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(0) AND clklatch(1).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(1) AND cpudata(0) AND NOT clklatch(1).LFBK)); clklatch_C(1) <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FTCPE_clklatch2: FTCPE port map (clklatch(2),clklatch_T(2),clklatch_C(2),NOT reset,'0'); clklatch_T(2) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(1) AND clklatch(2).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(0) AND clklatch(2).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(1) AND NOT cpudata(0) AND NOT clklatch(2).LFBK)); clklatch_C(2) <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FTCPE_clklatch3: FTCPE port map (clklatch(3),clklatch_T(3),clklatch_C(3),'0',NOT reset); clklatch_T(3) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(1) AND clklatch(3).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(0) AND clklatch(3).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(1) AND cpudata(0) AND NOT clklatch(3).LFBK)); clklatch_C(3) <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FDCPE_clocked_rnw: FDCPE port map (clocked_rnw,cpurnw,NOT cpuclk_OBUF/cpuclk_OBUF_D2__$INT.LFBK,'0',NOT reset); cpuclk <= NOT ((NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN)); cpuclk_OBUF/cpuclk_OBUF_D2__$INT <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FDCPE_diag: FDCPE port map (diag,'1',MyClockSync/slowdetected,diag_OBUF/diag_OBUF_RSTF,'0'); diag_OBUF/diag_OBUF_RSTF <= ((NOT reset) OR (extclkdel AND slowaccess.LFBK)); FDCPE_extclkdel: FDCPE port map (extclkdel,MyClock/phi0D5.LFBK,NOT fastclkby2,'0','0'); FTCPE_fastclkby2: FTCPE port map (fastclkby2,'1',NOT fastclkin,'0','0'); FTCPE_fastclkbydiv: FTCPE port map (fastclkbydiv,fastclkbydiv_T,NOT fastclkin,NOT fastclkbydiv/fastclkbydiv_RSTF__$INT,'0'); fastclkbydiv_T <= (NOT Mytiming/clkcounter(0).LFBK AND NOT Mytiming/clkcounter(1).LFBK AND NOT Mytiming/clkcounter(2).LFBK AND NOT Mytiming/clkcounter(3).LFBK); fastclkbydiv/fastclkbydiv_RSTF__$INT <= (NOT slowaccess AND reset); FDCPE_isorigdel: FDCPE port map (isorigdel,isorigdel_D,NOT cpuclk_OBUF/cpuclk_OBUF_D2__$INT.LFBK,NOT reset,'0'); isorigdel_D <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22)) OR (cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22)) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT bootrom AND slow64k) OR (cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22))); latchen <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag_OBUF.LFBK); norom <= (slowaccess AND isorigdel AND validaddrdel); nramcs(0) <= ((NOT reset) OR (cpuaddrin_64k(21)) OR (cpuaddrin_64k(20)) OR (cpuaddrin_64k(19)) OR (cpuaddrin_64k(23)) OR (cpuaddrin_64k(22)) OR (EXP5_.EXP) OR (NOT cpuvpa AND NOT cpuvda) OR (NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpurnw AND slow64k) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpurnw AND wprotect(1)) OR (cpuaddrin_2k(15) AND NOT cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND cpurnw) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND cpurnw)); nramcs(1) <= NOT (((NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND reset AND cpuvda AND fastclkbydiv) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND reset AND cpuvda AND diag.PIN) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND slowaccess AND reset AND cpuvpa) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND slowaccess AND reset AND cpuvda) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND reset AND cpuvpa AND fastclkbydiv) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND reset AND cpuvpa AND diag.PIN))); nromcs <= NOT (((NOT cpuaddrin_2k(15) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2) OR (NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND cpuaddrin_2k(12) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2) OR (cpuaddrin_2k(14) AND NOT cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (NOT cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2) OR (NOT cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (cpuaddrin_2k(13) AND NOT cpuaddrin_2k(11) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2) OR (cpuaddrin_2k(13) AND NOT cpuaddrin_2k(11) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND cpurnw AND cpuvda AND phi2) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND cpuvpa AND phi2 AND prgrom.LFBK) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND cpuvda AND phi2 AND prgrom.LFBK) OR (NOT cpuaddrin_2k(15) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND bootrom AND slowaccess AND reset AND cpurnw AND cpuvpa AND phi2))); nromwe <= NOT (((cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND reset AND NOT cpurnw AND cpuvda AND diag_OBUF.LFBK) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND NOT cpurnw AND cpuvpa) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND slowaccess AND reset AND NOT cpurnw AND cpuvda) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND reset AND NOT cpurnw AND cpuvpa AND fastclkbydiv) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND reset AND NOT cpurnw AND cpuvpa AND diag_OBUF.LFBK) OR (cpuaddrin_64k(21) AND cpuaddrin_64k(20) AND cpuaddrin_64k(19) AND cpuaddrin_64k(23) AND cpuaddrin_64k(22) AND reset AND NOT cpurnw AND cpuvda AND fastclkbydiv))); nslowbusclr <= NOT ((NOT MyClock/phi0D4.LFBK AND MyClock/phi0D5.LFBK)); nslowbusen <= (slowaccess AND isorigdel AND validaddrdel); nslowdataen <= ((NOT slowaccess) OR (NOT isorigdel) OR (NOT validaddrdel) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22))); FTCPE_prgrom: FTCPE port map (prgrom,prgrom_T,prgrom_C,NOT reset,'0'); prgrom_T <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(7) AND NOT prgrom.LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(7) AND prgrom.LFBK)); prgrom_C <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag_OBUF.LFBK); rnw <= NOT ((slowaccess AND NOT clocked_rnw.LFBK AND isorigdel.LFBK AND validaddrdel.LFBK)); FTCPE_slow64k: FTCPE port map (slow64k,slow64k_T,slow64k_C,'0',NOT reset); slow64k_T <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(5) AND NOT slow64k.LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(5) AND slow64k.LFBK)); slow64k_C <= (NOT fastclkbydiv AND NOT slowaccess.LFBK AND NOT diag.PIN); FDCPE_slowaccess: FDCPE port map (slowaccess,MyClockSync/slowdetected,NOT extclkdel,slowaccess/slowaccess_RSTF,'0'); slowaccess/slowaccess_RSTF <= ((MyClock/phi0D3 AND NOT MyClock/phi0D2 AND clocked_rnw.LFBK) OR (NOT MyClock/phi0D3 AND NOT clocked_rnw.LFBK AND MyClock/phi0D4.LFBK)); FTCPE_slowonly: FTCPE port map (slowonly,slowonly_T,slowonly_C,NOT reset,'0'); slowonly_T <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(4) AND NOT slowonly.LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(4) AND slowonly.LFBK)); slowonly_C <= (NOT slowaccess AND NOT fastclkbydiv AND NOT diag.PIN); FDCPE_validaddrdel: FDCPE port map (validaddrdel,validaddrdel_D,NOT cpuclk_OBUF/cpuclk_OBUF_D2__$INT.LFBK,NOT reset,'0'); validaddrdel_D <= (NOT cpuvpa AND NOT cpuvda); FTCPE_wprotect0: FTCPE port map (wprotect(0),wprotect_T(0),wprotect_C(0),NOT reset,'0'); wprotect_T(0) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(2) AND NOT wprotect(0).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(2) AND wprotect(0).LFBK)); wprotect_C(0) <= (NOT fastclkbydiv AND NOT slowaccess.LFBK AND NOT diag.PIN); FTCPE_wprotect1: FTCPE port map (wprotect(1),wprotect_T(1),wprotect_C(1),NOT reset,'0'); wprotect_T(1) <= ((cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND cpudata(3) AND NOT wprotect(1).LFBK) OR (cpuaddrin_2k(15) AND cpuaddrin_2k(14) AND cpuaddrin_2k(13) AND cpuaddrin_2k(11) AND cpuaddrin_16(3) AND cpuaddrin_16(2) AND cpuaddrin_16(1) AND cpuaddrin_16(0) AND NOT cpuaddrin_64k(21) AND NOT cpuaddrin_64k(20) AND NOT cpuaddrin_64k(19) AND NOT cpuaddrin_64k(18) AND NOT cpuaddrin_64k(17) AND NOT cpuaddrin_64k(16) AND NOT cpuaddrin_2k(12) AND NOT cpuaddr_ismyio AND NOT cpuaddrin_64k(23) AND NOT cpuaddrin_64k(22) AND NOT cpurnw AND NOT cpudata(3) AND wprotect(1).LFBK)); wprotect_C(1) <= (NOT fastclkbydiv AND NOT slowaccess.LFBK AND NOT diag.PIN); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95108-15-PC84 -------------------------------------------------------------- /11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \ | 12 74 | | 13 73 | | 14 72 | | 15 71 | | 16 70 | | 17 69 | | 18 68 | | 19 67 | | 20 66 | | 21 XC95108-15-PC84 65 | | 22 64 | | 23 63 | | 24 62 | | 25 61 | | 26 60 | | 27 59 | | 28 58 | | 29 57 | | 30 56 | | 31 55 | | 32 54 | \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 / -------------------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 cpuaddrin_2k<12> 43 nramcs<1> 2 cpuaddrin_2k<13> 44 TIE 3 cpuaddrin_2k<14> 45 TIE 4 cpuaddrin_2k<15> 46 TIE 5 cpuaddrin_2k<11> 47 TIE 6 cpuclk 48 TIE 7 nslowdataen 49 GND 8 GND 50 nromwe 9 TIE 51 diag 10 fastclkin 52 latchen 11 cpuvpa 53 nromcs 12 phi2 54 cpudata<1> 13 cpuvda 55 cpudata<0> 14 TIE 56 cpudata<3> 15 norom 57 cpudata<2> 16 GND 58 cpudata<4> 17 cpurnw 59 TDO 18 reset 60 GND 19 bootromin 61 cpudata<6> 20 nslowbusen 62 cpudata<7> 21 TIE 63 cpudata<5> 22 VCC 64 VCC 23 TIE 65 TIE 24 TIE 66 cpuaddrin_64k<23> 25 cpuaddr_ismyio 67 cpuaddrin_64k<22> 26 TIE 68 cpuaddrin_64k<21> 27 GND 69 cpuaddrin_64k<20> 28 TDI 70 cpuaddrin_64k<19> 29 TMS 71 cpuaddrin_64k<16> 30 TCK 72 cpuaddrin_64k<17> 31 TIE 73 VCC 32 nslowbusclr 74 TIE 33 rnw 75 cpuaddrin_64k<18> 34 TIE 76 TIE 35 TIE 77 TIE 36 TIE 78 VCC 37 TIE 79 TIE 38 VCC 80 TIE 39 rdy 81 cpuaddrin_16<1> 40 TIE 82 cpuaddrin_16<0> 41 nramcs<0> 83 cpuaddrin_16<3> 42 GND 84 cpuaddrin_16<2> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95108-15-PC84 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25