Design Name | PET816 |
Device, Speed (SpeedFile Version) | XC95108, -15 (3.0) |
Date Created | Tue Apr 20 19:36:31 2010 |
Created By | Timing Report Generator: version L.33 |
Copyright | Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Possible asynchronous logic: Clock pin 'bootrom.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<0>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<1>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<2>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'clklatch<3>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'clocked_rnw.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'isorigdel.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'validaddrdel.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'wprotect<0>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'wprotect<1>.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'MyClockSync/slowdetected.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'bogusok.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'prgrom.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'slow64k.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Possible asynchronous logic: Clock pin 'slowonly.CLKF' has multiple original clock nets 'fastclkbydiv.Q' 'slowaccess.Q' 'diag_OBUF.Q'. |
Performance Summary | |
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Min. Clock Period | 20.000 ns. |
Max. Clock Frequency (fSYSTEM) | 50.000 MHz. |
Limited by Cycle Time for fastclkbydiv.Q | |
Clock to Setup (tCYC) | 20.000 ns. |
Pad to Pad Delay (tPD) | 17.000 ns. |
Setup to Clock at the Pad (tSU) | 8.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 119.500 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
TS1003 | 0.0 | 0.0 | 0 | 0 |
TS1004 | 0.0 | 0.0 | 0 | 0 |
TS1005 | 0.0 | 0.0 | 0 | 0 |
TS1006 | 0.0 | 0.0 | 0 | 0 |
TS1007 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 20.0 | 53 | 53 |
AUTO_TS_P2P | 0.0 | 119.5 | 82 | 82 |
AUTO_TS_P2F | 0.0 | 13.0 | 259 | 259 |
AUTO_TS_F2P | 0.0 | 24.0 | 38 | 38 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
bogusok.Q to MyClockSync/slowdetected.D | 0.000 | 20.000 | -20.000 |
bootrom.Q to MyClockSync/slowdetected.D | 0.000 | 19.000 | -19.000 |
clklatch<1>.Q to Mytiming/clkcounter<1>.D | 0.000 | 19.000 | -19.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
fastclkin to norom | 0.000 | 119.500 | -119.500 |
fastclkin to nslowbusen | 0.000 | 119.500 | -119.500 |
fastclkin to nslowdataen | 0.000 | 119.500 | -119.500 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
cpuaddrin_2k<11> to MyClockSync/slowdetected.D | 0.000 | 13.000 | -13.000 |
cpuaddrin_2k<12> to MyClockSync/slowdetected.D | 0.000 | 13.000 | -13.000 |
cpuaddrin_2k<13> to MyClockSync/slowdetected.D | 0.000 | 13.000 | -13.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
bootrom.Q to nramcs<0> | 0.000 | 24.000 | -24.000 |
fastclkbydiv.Q to nramcs<0> | 0.000 | 24.000 | -24.000 |
slowaccess.Q to nramcs<0> | 0.000 | 24.000 | -24.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
fastclkby2.Q | 55.556 | Limited by Cycle Time for fastclkby2.Q |
MyClockSync/slowdetected.Q | 71.429 | Limited by Clock Pulse Width for MyClockSync/slowdetected.Q |
phi2 | 95.238 | Limited by Cycle Time for phi2 |
extclkdel.Q | 71.429 | Limited by Clock Pulse Width for extclkdel.Q |
fastclkin | 86.957 | Limited by Cycle Time for fastclkin |
fastclkbydiv.Q | 50.000 | Limited by Cycle Time for fastclkbydiv.Q |
slowaccess.Q | 50.000 | Limited by Cycle Time for slowaccess.Q |
diag_OBUF.Q | 50.000 | Limited by Cycle Time for diag_OBUF.Q |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
phi2 | -3.000 | 7.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
rdy | 8.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | -3.000 | 7.500 |
cpuaddrin_16<0> | -3.000 | 7.500 |
cpuaddrin_16<1> | -3.000 | 7.500 |
cpuaddrin_16<2> | -3.000 | 7.500 |
cpuaddrin_16<3> | -3.000 | 7.500 |
cpuaddrin_2k<11> | -3.000 | 22.500 |
cpuaddrin_2k<12> | -3.000 | 22.500 |
cpuaddrin_2k<13> | -3.000 | 22.500 |
cpuaddrin_2k<14> | -3.000 | 22.500 |
cpuaddrin_2k<15> | -3.000 | 22.500 |
cpuaddrin_64k<16> | -3.000 | 22.500 |
cpuaddrin_64k<17> | -3.000 | 22.500 |
cpuaddrin_64k<18> | -3.000 | 22.500 |
cpuaddrin_64k<19> | -3.000 | 22.500 |
cpuaddrin_64k<20> | -3.000 | 22.500 |
cpuaddrin_64k<21> | -3.000 | 22.500 |
cpuaddrin_64k<22> | -3.000 | 22.500 |
cpuaddrin_64k<23> | -3.000 | 22.500 |
cpudata<0> | -3.000 | 7.500 |
cpudata<1> | -3.000 | 7.500 |
cpudata<2> | -3.000 | 7.500 |
cpudata<3> | -3.000 | 7.500 |
cpudata<4> | -3.000 | 7.500 |
cpudata<5> | -3.000 | 7.500 |
cpudata<6> | -3.000 | 7.500 |
cpudata<7> | -3.000 | 7.500 |
cpurnw | -3.000 | 17.000 |
cpuvda | -12.500 | 22.500 |
cpuvpa | -12.500 | 23.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | 4.500 | 7.500 |
cpuaddrin_16<0> | 4.500 | 7.500 |
cpuaddrin_16<1> | 4.500 | 7.500 |
cpuaddrin_16<2> | 4.500 | 7.500 |
cpuaddrin_16<3> | 4.500 | 7.500 |
cpuaddrin_2k<11> | 4.500 | 22.500 |
cpuaddrin_2k<12> | 4.500 | 22.500 |
cpuaddrin_2k<13> | 4.500 | 22.500 |
cpuaddrin_2k<14> | 4.500 | 22.500 |
cpuaddrin_2k<15> | 4.500 | 22.500 |
cpuaddrin_64k<16> | 4.500 | 22.500 |
cpuaddrin_64k<17> | 4.500 | 22.500 |
cpuaddrin_64k<18> | 4.500 | 22.500 |
cpuaddrin_64k<19> | 4.500 | 22.500 |
cpuaddrin_64k<20> | 4.500 | 22.500 |
cpuaddrin_64k<21> | 4.500 | 22.500 |
cpuaddrin_64k<22> | 4.500 | 22.500 |
cpuaddrin_64k<23> | 4.500 | 22.500 |
cpudata<0> | -3.000 | 7.500 |
cpudata<1> | -3.000 | 7.500 |
cpudata<2> | 4.500 | 0.000 |
cpudata<3> | 4.500 | 0.000 |
cpudata<4> | -3.000 | 7.500 |
cpudata<5> | 4.500 | 0.000 |
cpudata<6> | -3.000 | 7.500 |
cpudata<7> | -3.000 | 7.500 |
cpurnw | 4.500 | 17.000 |
cpuvda | -12.500 | 22.500 |
cpuvpa | -12.500 | 23.500 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
cpuaddr_ismyio | 4.500 | 5.500 |
cpuaddrin_16<0> | 4.500 | 5.500 |
cpuaddrin_16<1> | 4.500 | 5.500 |
cpuaddrin_16<2> | 4.500 | 5.500 |
cpuaddrin_16<3> | 4.500 | 5.500 |
cpuaddrin_2k<11> | 4.500 | 20.500 |
cpuaddrin_2k<12> | 4.500 | 20.500 |
cpuaddrin_2k<13> | 4.500 | 20.500 |
cpuaddrin_2k<14> | 4.500 | 20.500 |
cpuaddrin_2k<15> | 4.500 | 20.500 |
cpuaddrin_64k<16> | 4.500 | 20.500 |
cpuaddrin_64k<17> | 4.500 | 20.500 |
cpuaddrin_64k<18> | 4.500 | 20.500 |
cpuaddrin_64k<19> | 4.500 | 20.500 |
cpuaddrin_64k<20> | 4.500 | 20.500 |
cpuaddrin_64k<21> | 4.500 | 20.500 |
cpuaddrin_64k<22> | 4.500 | 20.500 |
cpuaddrin_64k<23> | 4.500 | 20.500 |
cpudata<0> | -1.000 | 5.500 |
cpudata<1> | -1.000 | 5.500 |
cpudata<2> | -1.000 | 5.500 |
cpudata<3> | -1.000 | 5.500 |
cpudata<4> | -1.000 | 5.500 |
cpudata<5> | -1.000 | 5.500 |
cpudata<6> | -1.000 | 5.500 |
cpudata<7> | 4.500 | 0.000 |
cpurnw | 4.500 | 15.000 |
cpuvda | -10.500 | 20.500 |
cpuvpa | -10.500 | 21.500 |
Destination Pad | Clock (edge) to Pad |
---|---|
norom | 119.500 |
nslowbusen | 119.500 |
nslowdataen | 119.500 |
nramcs<0> | 112.000 |
rnw | 112.000 |
nromcs | 111.000 |
nramcs<1> | 97.000 |
cpuclk | 96.000 |
latchen | 91.500 |
nromwe | 91.500 |
diag | 81.000 |
nslowbusclr | 31.500 |
Source | Destination | Delay |
---|---|---|
MyClock/phi0D3.Q | MyClock/phi0D4.D | 18.000 |
MyClock/phi0D1.Q | MyClock/phi0D2.D | 10.500 |
MyClock/phi0D2.Q | MyClock/phi0D3.D | 10.500 |
MyClock/phi0D4.Q | MyClock/phi0D5.D | 10.500 |
MyClock/phi0D5.Q | extclkdel.D | 10.500 |
Source | Destination | Delay |
---|---|---|
MyClockSync/slowdone.Q | MyClockSync/slowdone.D | 10.500 |
Source | Destination | Delay |
---|---|---|
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<1>.D | 11.500 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<2>.D | 11.500 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<3>.D | 11.500 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<1>.D | 11.500 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<2>.D | 11.500 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<3>.D | 11.500 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<1>.D | 11.500 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<2>.D | 11.500 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<3>.D | 11.500 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<1>.D | 11.500 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<2>.D | 11.500 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<3>.D | 11.500 |
Mytiming/clkcounter<0>.Q | Mytiming/clkcounter<0>.D | 10.500 |
Mytiming/clkcounter<0>.Q | fastclkbydiv.D | 10.500 |
Mytiming/clkcounter<1>.Q | Mytiming/clkcounter<0>.D | 10.500 |
Mytiming/clkcounter<1>.Q | fastclkbydiv.D | 10.500 |
Mytiming/clkcounter<2>.Q | Mytiming/clkcounter<0>.D | 10.500 |
Mytiming/clkcounter<2>.Q | fastclkbydiv.D | 10.500 |
Mytiming/clkcounter<3>.Q | Mytiming/clkcounter<0>.D | 10.500 |
Mytiming/clkcounter<3>.Q | fastclkbydiv.D | 10.500 |
Source | Destination | Delay |
---|---|---|
bogusok.Q | MyClockSync/slowdetected.D | 20.000 |
bootrom.Q | MyClockSync/slowdetected.D | 19.000 |
slow64k.Q | MyClockSync/slowdetected.D | 19.000 |
bootrom.Q | isorigdel.D | 18.000 |
slow64k.Q | isorigdel.D | 18.000 |
slowonly.Q | MyClockSync/slowdetected.D | 18.000 |
bogusok.Q | bogusok.D | 10.500 |
bootrom.Q | bootrom.D | 10.500 |
clklatch<0>.Q | clklatch<0>.D | 10.500 |
clklatch<1>.Q | clklatch<1>.D | 10.500 |
clklatch<2>.Q | clklatch<2>.D | 10.500 |
clklatch<3>.Q | clklatch<3>.D | 10.500 |
prgrom.Q | prgrom.D | 10.500 |
slow64k.Q | slow64k.D | 10.500 |
slowonly.Q | slowonly.D | 10.500 |
wprotect<0>.Q | wprotect<0>.D | 10.500 |
wprotect<1>.Q | wprotect<1>.D | 10.500 |
Source | Destination | Delay |
---|---|---|
bogusok.Q | MyClockSync/slowdetected.D | 20.000 |
bootrom.Q | MyClockSync/slowdetected.D | 19.000 |
slow64k.Q | MyClockSync/slowdetected.D | 19.000 |
bootrom.Q | isorigdel.D | 18.000 |
slow64k.Q | isorigdel.D | 18.000 |
slowonly.Q | MyClockSync/slowdetected.D | 18.000 |
bogusok.Q | bogusok.D | 10.500 |
bootrom.Q | bootrom.D | 10.500 |
clklatch<0>.Q | clklatch<0>.D | 10.500 |
clklatch<1>.Q | clklatch<1>.D | 10.500 |
clklatch<2>.Q | clklatch<2>.D | 10.500 |
clklatch<3>.Q | clklatch<3>.D | 10.500 |
prgrom.Q | prgrom.D | 10.500 |
slow64k.Q | slow64k.D | 10.500 |
slowonly.Q | slowonly.D | 10.500 |
wprotect<0>.Q | wprotect<0>.D | 10.500 |
wprotect<1>.Q | wprotect<1>.D | 10.500 |
Source | Destination | Delay |
---|---|---|
bogusok.Q | MyClockSync/slowdetected.D | 20.000 |
bootrom.Q | MyClockSync/slowdetected.D | 19.000 |
slow64k.Q | MyClockSync/slowdetected.D | 19.000 |
bootrom.Q | isorigdel.D | 18.000 |
slow64k.Q | isorigdel.D | 18.000 |
slowonly.Q | MyClockSync/slowdetected.D | 18.000 |
bogusok.Q | bogusok.D | 10.500 |
bootrom.Q | bootrom.D | 10.500 |
clklatch<0>.Q | clklatch<0>.D | 10.500 |
clklatch<1>.Q | clklatch<1>.D | 10.500 |
clklatch<2>.Q | clklatch<2>.D | 10.500 |
clklatch<3>.Q | clklatch<3>.D | 10.500 |
prgrom.Q | prgrom.D | 10.500 |
slow64k.Q | slow64k.D | 10.500 |
slowonly.Q | slowonly.D | 10.500 |
wprotect<0>.Q | wprotect<0>.D | 10.500 |
wprotect<1>.Q | wprotect<1>.D | 10.500 |
Source Pad | Destination Pad | Delay |
---|---|---|
cpuaddrin_2k<13> | nramcs<0> | 17.000 |
cpuaddrin_2k<14> | nramcs<0> | 17.000 |
cpuaddrin_2k<15> | nramcs<0> | 17.000 |
cpuaddrin_64k<16> | nramcs<0> | 17.000 |
cpuaddrin_64k<17> | nramcs<0> | 17.000 |
cpuaddrin_64k<18> | nramcs<0> | 17.000 |
cpurnw | nramcs<0> | 17.000 |
cpuaddrin_2k<11> | nromcs | 16.000 |
cpuaddrin_2k<12> | nromcs | 16.000 |
cpuaddrin_2k<13> | nromcs | 16.000 |
cpuaddrin_2k<14> | nromcs | 16.000 |
cpuaddrin_2k<15> | nromcs | 16.000 |
cpuaddrin_64k<16> | nromcs | 16.000 |
cpuaddrin_64k<17> | nromcs | 16.000 |
cpuaddrin_64k<18> | nromcs | 16.000 |
cpuaddrin_64k<19> | nramcs<0> | 16.000 |
cpuaddrin_64k<19> | nramcs<1> | 16.000 |
cpuaddrin_64k<19> | nromcs | 16.000 |
cpuaddrin_64k<19> | nromwe | 16.000 |
cpuaddrin_64k<20> | nramcs<0> | 16.000 |
cpuaddrin_64k<20> | nramcs<1> | 16.000 |
cpuaddrin_64k<20> | nromcs | 16.000 |
cpuaddrin_64k<20> | nromwe | 16.000 |
cpuaddrin_64k<21> | nramcs<0> | 16.000 |
cpuaddrin_64k<21> | nramcs<1> | 16.000 |
cpuaddrin_64k<21> | nromcs | 16.000 |
cpuaddrin_64k<21> | nromwe | 16.000 |
cpuaddrin_64k<22> | nramcs<0> | 16.000 |
cpuaddrin_64k<22> | nramcs<1> | 16.000 |
cpuaddrin_64k<22> | nromcs | 16.000 |
cpuaddrin_64k<22> | nromwe | 16.000 |
cpuaddrin_64k<23> | nramcs<0> | 16.000 |
cpuaddrin_64k<23> | nramcs<1> | 16.000 |
cpuaddrin_64k<23> | nromcs | 16.000 |
cpuaddrin_64k<23> | nromwe | 16.000 |
cpurnw | nromcs | 16.000 |
cpurnw | nromwe | 16.000 |
cpuvda | nramcs<0> | 16.000 |
cpuvda | nramcs<1> | 16.000 |
cpuvda | nromcs | 16.000 |
cpuvda | nromwe | 16.000 |
cpuvpa | nramcs<0> | 16.000 |
cpuvpa | nromcs | 16.000 |
phi2 | nromcs | 16.000 |
reset | nramcs<1> | 16.000 |
reset | nromcs | 16.000 |
reset | nromwe | 16.000 |
cpuaddr_ismyio | nslowdataen | 15.000 |
cpuaddrin_16<0> | nslowdataen | 15.000 |
cpuaddrin_16<1> | nslowdataen | 15.000 |
cpuaddrin_16<2> | nslowdataen | 15.000 |
cpuaddrin_16<3> | nslowdataen | 15.000 |
cpuaddrin_2k<11> | nramcs<0> | 15.000 |
cpuaddrin_2k<11> | nslowdataen | 15.000 |
cpuaddrin_2k<12> | nramcs<0> | 15.000 |
cpuaddrin_2k<12> | nslowdataen | 15.000 |
cpuaddrin_2k<13> | nslowdataen | 15.000 |
cpuaddrin_2k<14> | nslowdataen | 15.000 |
cpuaddrin_2k<15> | nslowdataen | 15.000 |
cpuaddrin_64k<16> | nslowdataen | 15.000 |
cpuaddrin_64k<17> | nslowdataen | 15.000 |
cpuaddrin_64k<18> | nslowdataen | 15.000 |
cpuaddrin_64k<19> | nslowdataen | 15.000 |
cpuaddrin_64k<20> | nslowdataen | 15.000 |
cpuaddrin_64k<21> | nslowdataen | 15.000 |
cpuaddrin_64k<22> | nslowdataen | 15.000 |
cpuaddrin_64k<23> | nslowdataen | 15.000 |
cpuvpa | nramcs<1> | 15.000 |
cpuvpa | nromwe | 15.000 |
reset | nramcs<0> | 15.000 |