I've been reading some info on Verilog recently and it seems that Verilog (IEEE 1364-2005) standard has expanded to incorporate the best features of VHDL into a single Verilog HDL (IEEE Standard 1800-2009) called SystemVerilog. It is Wiki'd here.

I noticed in Xilinx ISE 13.2 under Design Properties it gives the choice for VHDL Source Analysis Standard to be either VHDL-93 or VHDL-200X, even though Verilog was chosen as preferred language. Is there any relation? Can anyone comment on this? Is Xilinx headed towards incorporating SystemVerilog?

Hi EEYe
What do mean by verilog being preferred language? I don't think Xilinx prefer anything - they support everything, because they just want to sell lots of FPGAs.

Verilog/VHDL is a long-running question which people can get quite heated about - usually people have a strong preference. I think we've covered this before - here was my post.

Cheers
Ed

By preferred, I meant what is chosen at the beginning of a project...


I've been reading abit more and not too much is mentioned in Xilinx forums, except that a separate license is required and third party software like Synopsys or Mentor is needed to generate the .sv file, so most likely Xilinx XST will not be supporting systemverilog anytime soon.

Are you kidding? It doesn't even support Verilog-2001.

(I discovered this by trying to define a macro with parameters, but the preprocessor would have nothing to do with it.)